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* [PATCH] clk: renesas: r8a779[56]x: add MLP clock
@ 2021-09-29 21:34 Nikita Yushchenko
  2021-10-05 15:53 ` Geert Uytterhoeven
  0 siblings, 1 reply; 4+ messages in thread
From: Nikita Yushchenko @ 2021-09-29 21:34 UTC (permalink / raw)
  To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
  Cc: linux-renesas-soc, linux-clk, linux-kernel, Andrey Gusakov,
	Nikita Yushchenko

From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>

Add clocks for MLP module on Renesas H3 and M3.

Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c  | 1 +
 drivers/clk/renesas/r8a7796-cpg-mssr.c  | 1 +
 drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index c32d2c678046..d6b1d0148bfd 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -229,6 +229,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
 	DEF_MOD("lvds",			 727,	R8A7795_CLK_S0D4),
 	DEF_MOD("hdmi1",		 728,	R8A7795_CLK_HDMI),
 	DEF_MOD("hdmi0",		 729,	R8A7795_CLK_HDMI),
+	DEF_MOD("mlp",			 802,	R8A7795_CLK_S2D1),
 	DEF_MOD("vin7",			 804,	R8A7795_CLK_S0D2),
 	DEF_MOD("vin6",			 805,	R8A7795_CLK_S0D2),
 	DEF_MOD("vin5",			 806,	R8A7795_CLK_S0D2),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 41593c126faf..9c22977e42c2 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
 	DEF_MOD("du0",			 724,	R8A7796_CLK_S2D1),
 	DEF_MOD("lvds",			 727,	R8A7796_CLK_S2D1),
 	DEF_MOD("hdmi0",		 729,	R8A7796_CLK_HDMI),
+	DEF_MOD("mlp",			 802,	R8A7796_CLK_S2D1),
 	DEF_MOD("vin7",			 804,	R8A7796_CLK_S0D2),
 	DEF_MOD("vin6",			 805,	R8A7796_CLK_S0D2),
 	DEF_MOD("vin5",			 806,	R8A7796_CLK_S0D2),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index bc1be8bcbbe4..52c5da26b756 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -205,6 +205,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
 	DEF_MOD("lvds",			727,	R8A77965_CLK_S2D1),
 	DEF_MOD("hdmi0",		729,	R8A77965_CLK_HDMI),
 
+	DEF_MOD("mlp",			802,	R8A77965_CLK_S2D1),
 	DEF_MOD("vin7",			804,	R8A77965_CLK_S0D2),
 	DEF_MOD("vin6",			805,	R8A77965_CLK_S0D2),
 	DEF_MOD("vin5",			806,	R8A77965_CLK_S0D2),
-- 
2.30.2


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] clk: renesas: r8a779[56]x: add MLP clock
  2021-09-29 21:34 [PATCH] clk: renesas: r8a779[56]x: add MLP clock Nikita Yushchenko
@ 2021-10-05 15:53 ` Geert Uytterhoeven
  2021-10-07 20:09   ` Nikita Yushchenko
  0 siblings, 1 reply; 4+ messages in thread
From: Geert Uytterhoeven @ 2021-10-05 15:53 UTC (permalink / raw)
  To: Nikita Yushchenko
  Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
	Linux-Renesas, linux-clk, Linux Kernel Mailing List,
	Andrey Gusakov

Hi Nikita,

On Wed, Sep 29, 2021 at 11:35 PM Nikita Yushchenko
<nikita.yoush@cogentembedded.com> wrote:
> From: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
>
> Add clocks for MLP module on Renesas H3 and M3.
>
> Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -229,6 +229,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
>         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
>         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
>         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
> +       DEF_MOD("mlp",                   802,   R8A7795_CLK_S2D1),
>         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
>         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
>         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 41593c126faf..9c22977e42c2 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
>         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
>         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
>         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
> +       DEF_MOD("mlp",                   802,   R8A7796_CLK_S2D1),
>         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
>         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
>         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index bc1be8bcbbe4..52c5da26b756 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -205,6 +205,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
>         DEF_MOD("lvds",                 727,    R8A77965_CLK_S2D1),
>         DEF_MOD("hdmi0",                729,    R8A77965_CLK_HDMI),
>
> +       DEF_MOD("mlp",                  802,    R8A77965_CLK_S2D1),
>         DEF_MOD("vin7",                 804,    R8A77965_CLK_S0D2),
>         DEF_MOD("vin6",                 805,    R8A77965_CLK_S0D2),
>         DEF_MOD("vin5",                 806,    R8A77965_CLK_S0D2),

These additions look fine to me.  I'm only wondering about the
actual parent clocks, which are not well-documented in the Hardware
User's Manual.
It does say that MLP uses the Audio main bus (AXI).
The related AUDIO-DMAC uses S1D2, which runs at 266 MHz, while S2D1
runs at 400 MHz?

BTW, do you plan to enable full support for MLP in the upstream kernel?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] clk: renesas: r8a779[56]x: add MLP clock
  2021-10-05 15:53 ` Geert Uytterhoeven
@ 2021-10-07 20:09   ` Nikita Yushchenko
  2021-10-08  6:57     ` Geert Uytterhoeven
  0 siblings, 1 reply; 4+ messages in thread
From: Nikita Yushchenko @ 2021-10-07 20:09 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
	Linux-Renesas, linux-clk, Linux Kernel Mailing List,
	Andrey Gusakov

> These additions look fine to me.  I'm only wondering about the
> actual parent clocks, which are not well-documented in the Hardware
> User's Manual.
> It does say that MLP uses the Audio main bus (AXI).
> The related AUDIO-DMAC uses S1D2, which runs at 266 MHz, while S2D1
> runs at 400 MHz?

This patch was included in this form into Renesas BSP for years.

Indeed, the information on the parent clock is missing in the manual, and can be inexact here. I've sent 
a question to our contact at Renesas but not sure they will reply.

But, AFAIU, these parent clocks are not software-controlled, so having them wrong does not result in any 
issues other than inexact information exported via sysfs/debugfs.

> BTW, do you plan to enable full support for MLP in the upstream kernel?

Yes, we are upstreaming full KF board support now.

Nikita

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] clk: renesas: r8a779[56]x: add MLP clock
  2021-10-07 20:09   ` Nikita Yushchenko
@ 2021-10-08  6:57     ` Geert Uytterhoeven
  0 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2021-10-08  6:57 UTC (permalink / raw)
  To: Nikita Yushchenko
  Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
	Linux Kernel Mailing List, Andrey Gusakov

Hi Nikita,

On Thu, Oct 7, 2021 at 10:09 PM Nikita Yushchenko
<nikita.yoush@cogentembedded.com> wrote:
> > These additions look fine to me.  I'm only wondering about the
> > actual parent clocks, which are not well-documented in the Hardware
> > User's Manual.
> > It does say that MLP uses the Audio main bus (AXI).
> > The related AUDIO-DMAC uses S1D2, which runs at 266 MHz, while S2D1
> > runs at 400 MHz?
>
> This patch was included in this form into Renesas BSP for years.
>
> Indeed, the information on the parent clock is missing in the manual, and can be inexact here. I've sent
> a question to our contact at Renesas but not sure they will reply.
>
> But, AFAIU, these parent clocks are not software-controlled, so having them wrong does not result in any
> issues other than inexact information exported via sysfs/debugfs.

True.  So in case we don't get feedback, I'll take this patch as-is.

> > BTW, do you plan to enable full support for MLP in the upstream kernel?
>
> Yes, we are upstreaming full KF board support now.

I'm happy to hear that, thanks a lot!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-10-08  6:57 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-09-29 21:34 [PATCH] clk: renesas: r8a779[56]x: add MLP clock Nikita Yushchenko
2021-10-05 15:53 ` Geert Uytterhoeven
2021-10-07 20:09   ` Nikita Yushchenko
2021-10-08  6:57     ` Geert Uytterhoeven

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