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[79.139.163.57]) by smtp.gmail.com with ESMTPSA id j18sm2101125lfu.84.2021.10.05.16.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 16:01:05 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , Rob Herring Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 0/7] tegra20-emc: Identify memory chip by LPDDR configuration Date: Wed, 6 Oct 2021 02:00:02 +0300 Message-Id: <20211005230009.3635-1-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support memory chip identification by LPDDR2 configuration, which is needed by ASUS Transformer TF101 tablet device that doesn't store RAMCODE in Tegra's NVMEM. Changelog: v4: - Moved DDR bindings directory to memory-controllers/, like it was suggested by Krzysztof Kozlowski. - Converted existing LPDDR2 binding to schema and utilized it, like it was requested by Krzysztof Kozlowski. - Added Elpida B8132B2PB-6D-F compatible. - Made code changes that were requested by Krzysztof Kozlowski. v3: - Corrected sub-node name in tegra20-emc.yaml. v2: - Added separate binding for standard LPDDR2 properties, like it was suggested by Krzysztof Kozlowski. - Switched Tegra binding to use new lpddr2-configuration sub-node that contains the standard properties. - Extended commit message of the "emc: Document new LPDDR2 sub-node" patch, telling how the properties are supposed to be used, which was requested by Krzysztof Kozlowski. - Added new common helpers for parsing LPDDR2 properties and made tegra20-emc driver to use these helpers. Dmitry Osipenko (7): dt-bindings: Relocate DDR bindings dt-bindings: memory: lpddr2: Convert to schema dt-bindings: memory: lpddr2: Add revision-id properties dt-bindings: memory: lpddr2: Document Elpida B8132B2PB-6D-F dt-bindings: memory: tegra20: emc: Document new LPDDR2 sub-node memory: Add LPDDR2 configuration helpers memory: tegra20-emc: Support matching timings by LPDDR2 configuration .../devicetree/bindings/ddr/lpddr2.txt | 102 --------- .../memory-controllers/ddr/jedec,lpddr2.yaml | 208 ++++++++++++++++++ .../ddr/lpddr2-timings.txt | 0 .../ddr/lpddr3-timings.txt | 0 .../{ => memory-controllers}/ddr/lpddr3.txt | 0 .../nvidia,tegra20-emc.yaml | 23 +- drivers/memory/jedec_ddr.h | 46 ++++ drivers/memory/jedec_ddr_data.c | 41 ++++ drivers/memory/of_memory.c | 88 ++++++++ drivers/memory/of_memory.h | 9 + drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra20-emc.c | 199 +++++++++++++++-- 12 files changed, 599 insertions(+), 118 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ddr/lpddr2.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr2-timings.txt (100%) rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3-timings.txt (100%) rename Documentation/devicetree/bindings/{ => memory-controllers}/ddr/lpddr3.txt (100%) -- 2.32.0