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* [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-30 19:41   ` Limonciello, Mario
  2021-11-25 11:04 ` [PATCH v4 2/7] drivers: acpi: acpi_apd: Remove unused device property "is-rv" Ajit Kumar Pandey
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Michael Turquette, open list

FCH controller clock configuration slightly differs across AMD's
SOC architectures. Newer family of SOC only support a 48MHz fixed
clock while older family has a clk_mux to choose 48MHz and 25MHz.
At present fixed clk support is only enabled for RV architecture
using "is-rv" device property initialized from boot loader. This
limit 48MHz fixed clock gate support to RV platform unless we add
similar device property in boot loader for other architecture.

Add pci_device_id table with Raven platform id and replace "is-rv"
device property check with pci id match to support 48MHz fixed clk
support. This enhanced flexibility to enable fixed 48MHz fch clock
framework on other architectures by simply adding new entries into
pci_device_id table. Also replace RV with FIXED as generic naming
convention across all platforms.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 41 ++++++++++++++++++++++++++++++---------
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 8f7c5142b0f0..de556b03e184 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: MIT
 /*
- * clock framework for AMD Stoney based clocks
+ * clock framework for AMD FCH controller block
  *
  * Copyright 2018 Advanced Micro Devices, Inc.
  */
@@ -8,6 +8,7 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/pci.h>
 #include <linux/platform_data/clk-fch.h>
 #include <linux/platform_device.h>
 
@@ -26,22 +27,37 @@
 #define ST_CLK_GATE	3
 #define ST_MAX_CLKS	4
 
-#define RV_CLK_48M	0
-#define RV_CLK_GATE	1
-#define RV_MAX_CLKS	2
+#define CLK_48M_FIXED	0
+#define CLK_GATE_FIXED	1
+#define CLK_MAX_FIXED	2
+
+/* List of supported CPU ids for fixed clk */
+#define AMD_CPU_ID_RV			0x15D0
 
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
 
+static const struct pci_device_id soc_pci_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
+	{ }
+};
+
 static int fch_clk_probe(struct platform_device *pdev)
 {
 	struct fch_clk_data *fch_data;
+	struct pci_dev *rdev;
 
 	fch_data = dev_get_platdata(&pdev->dev);
 	if (!fch_data || !fch_data->base)
 		return -EINVAL;
 
-	if (!fch_data->is_rv) {
+	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
+	if (!rdev) {
+		dev_err(&pdev->dev, "FCH device not found\n");
+		return -ENODEV;
+	}
+
+	if (!pci_match_id(soc_pci_ids, rdev)) {
 		hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
 			NULL, 0, 48000000);
 		hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
@@ -61,17 +77,18 @@ static int fch_clk_probe(struct platform_device *pdev)
 		devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
 			"oscout1", NULL);
 	} else {
-		hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
+		hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
 			NULL, 0, 48000000);
 
-		hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
+		hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
 			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
 			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
 
-		devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
+		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
 			"oscout1", NULL);
 	}
 
+	pci_dev_put(rdev);
 	return 0;
 }
 
@@ -79,14 +96,20 @@ static int fch_clk_remove(struct platform_device *pdev)
 {
 	int i, clks;
 	struct fch_clk_data *fch_data;
+	struct pci_dev *rdev;
 
 	fch_data = dev_get_platdata(&pdev->dev);
 
-	clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
+	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
+	if (!rdev)
+		return -ENODEV;
+
+	clks = pci_match_id(soc_pci_ids, rdev) ? CLK_MAX_FIXED : ST_MAX_CLKS;
 
 	for (i = 0; i < clks; i++)
 		clk_hw_unregister(hws[i]);
 
+	pci_dev_put(rdev);
 	return 0;
 }
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 2/7] drivers: acpi: acpi_apd: Remove unused device property "is-rv"
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
  2021-11-25 11:04 ` [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 3/7] ACPI: APD: Add a fmw property clk-name Ajit Kumar Pandey
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Len Brown, open list:ACPI, open list

Initially "is-rv" device property is added for 48MHz fixed clock
support on Raven or RV architecture. It's unused now as we moved
to pci device_id based selection to extend such support on other
architectures. This change removed unused code from acpi driver.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/acpi/acpi_apd.c               | 3 ---
 include/linux/platform_data/clk-fch.h | 1 -
 2 files changed, 4 deletions(-)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index 6e02448d15d9..6913e9712852 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -87,9 +87,6 @@ static int fch_misc_setup(struct apd_private_data *pdata)
 	if (ret < 0)
 		return -ENOENT;
 
-	if (!acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj))
-		clk_data->is_rv = obj->integer.value;
-
 	list_for_each_entry(rentry, &resource_list, node) {
 		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
 					      resource_size(rentry->res));
diff --git a/include/linux/platform_data/clk-fch.h b/include/linux/platform_data/clk-fch.h
index b9f682459f08..850ca776156d 100644
--- a/include/linux/platform_data/clk-fch.h
+++ b/include/linux/platform_data/clk-fch.h
@@ -12,7 +12,6 @@
 
 struct fch_clk_data {
 	void __iomem *base;
-	u32 is_rv;
 };
 
 #endif /* __CLK_FCH_H */
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 3/7] ACPI: APD: Add a fmw property clk-name
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
  2021-11-25 11:04 ` [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 2/7] drivers: acpi: acpi_apd: Remove unused device property "is-rv" Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 4/7] clk: x86: Use dynamic con_id string during clk registration Ajit Kumar Pandey
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Len Brown, open list:ACPI, open list

Add a new device property to fetch clk-name from firmware.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/acpi/acpi_apd.c               | 10 ++++++++++
 include/linux/platform_data/clk-fch.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index 6913e9712852..2b958b426b03 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -87,6 +87,16 @@ static int fch_misc_setup(struct apd_private_data *pdata)
 	if (ret < 0)
 		return -ENOENT;
 
+	if (!acpi_dev_get_property(adev, "clk-name", ACPI_TYPE_STRING, &obj)) {
+		clk_data->name = devm_kzalloc(&adev->dev, obj->string.length,
+					      GFP_KERNEL);
+
+		strcpy(clk_data->name, obj->string.pointer);
+	} else {
+		/* Set default name to mclk if entry missing in firmware */
+		clk_data->name = "mclk";
+	}
+
 	list_for_each_entry(rentry, &resource_list, node) {
 		clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
 					      resource_size(rentry->res));
diff --git a/include/linux/platform_data/clk-fch.h b/include/linux/platform_data/clk-fch.h
index 850ca776156d..11a2a23fd9b2 100644
--- a/include/linux/platform_data/clk-fch.h
+++ b/include/linux/platform_data/clk-fch.h
@@ -12,6 +12,7 @@
 
 struct fch_clk_data {
 	void __iomem *base;
+	char *name;
 };
 
 #endif /* __CLK_FCH_H */
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 4/7] clk: x86: Use dynamic con_id string during clk registration
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
                   ` (2 preceding siblings ...)
  2021-11-25 11:04 ` [PATCH v4 3/7] ACPI: APD: Add a fmw property clk-name Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE Ajit Kumar Pandey
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Michael Turquette, open list

Replace hard coded con_id string with fch_data->name. We have clk
consumers looking up with different clock names, hence use dynamic
con_id string during clk lookup registration. fch_data->name will
be initialized in acpi driver based on fmw property value.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index de556b03e184..7c55e129779a 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -85,7 +85,7 @@ static int fch_clk_probe(struct platform_device *pdev)
 			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
 
 		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
-			"oscout1", NULL);
+					    fch_data->name, NULL);
 	}
 
 	pci_dev_put(rdev);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
                   ` (3 preceding siblings ...)
  2021-11-25 11:04 ` [PATCH v4 4/7] clk: x86: Use dynamic con_id string during clk registration Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 6/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Renoir platform Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 7/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Stoneyridge Ajit Kumar Pandey
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Michael Turquette, open list

In newer SoC we have to clear bit for disabling 48MHz oscillator
clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable
and disable of 48MHz clock.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 7c55e129779a..484fbb158e5b 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -82,7 +82,7 @@ static int fch_clk_probe(struct platform_device *pdev)
 
 		hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
 			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
-			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
+			OSCCLKENB, 0, NULL);
 
 		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
 					    fch_data->name, NULL);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 6/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Renoir platform
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
                   ` (4 preceding siblings ...)
  2021-11-25 11:04 ` [PATCH v4 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  2021-11-25 11:04 ` [PATCH v4 7/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Stoneyridge Ajit Kumar Pandey
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Michael Turquette, open list

Add renoir SOC pci root port id into pci_device_id table to enable 48
MHz fixed fch clock support on renoir platforms.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 484fbb158e5b..8747212cd289 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -33,12 +33,14 @@
 
 /* List of supported CPU ids for fixed clk */
 #define AMD_CPU_ID_RV			0x15D0
+#define AMD_CPU_ID_RN			0x1630
 
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
 
 static const struct pci_device_id fch_pci_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 	{ }
 };
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v4 7/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Stoneyridge
       [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
                   ` (5 preceding siblings ...)
  2021-11-25 11:04 ` [PATCH v4 6/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Renoir platform Ajit Kumar Pandey
@ 2021-11-25 11:04 ` Ajit Kumar Pandey
  6 siblings, 0 replies; 9+ messages in thread
From: Ajit Kumar Pandey @ 2021-11-25 11:04 UTC (permalink / raw)
  To: sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Mario.Limonciello, Ajit Kumar Pandey,
	Michael Turquette, open list

Add stoney ridge SOC pci root port id into pci_device_id table to
enable 48 MHz fixed fch clock support on Stoneyridge platforms.

Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
---
 drivers/clk/x86/clk-fch.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
index 8747212cd289..e3cd176a49e8 100644
--- a/drivers/clk/x86/clk-fch.c
+++ b/drivers/clk/x86/clk-fch.c
@@ -34,6 +34,7 @@
 /* List of supported CPU ids for fixed clk */
 #define AMD_CPU_ID_RV			0x15D0
 #define AMD_CPU_ID_RN			0x1630
+#define AMD_CPU_ID_ST			0x1576
 
 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
 static struct clk_hw *hws[ST_MAX_CLKS];
@@ -41,6 +42,7 @@ static struct clk_hw *hws[ST_MAX_CLKS];
 static const struct pci_device_id fch_pci_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_ST) },
 	{ }
 };
 
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC
  2021-11-25 11:04 ` [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC Ajit Kumar Pandey
@ 2021-11-30 19:41   ` Limonciello, Mario
  2021-12-10  1:45     ` Stephen Boyd
  0 siblings, 1 reply; 9+ messages in thread
From: Limonciello, Mario @ 2021-11-30 19:41 UTC (permalink / raw)
  To: Ajit Kumar Pandey, sboyd, rafael, linux-clk
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Michael Turquette, open list

On 11/25/2021 05:04, Ajit Kumar Pandey wrote:
> FCH controller clock configuration slightly differs across AMD's
> SOC architectures. Newer family of SOC only support a 48MHz fixed
> clock while older family has a clk_mux to choose 48MHz and 25MHz.
> At present fixed clk support is only enabled for RV architecture
> using "is-rv" device property initialized from boot loader. This
> limit 48MHz fixed clock gate support to RV platform unless we add
> similar device property in boot loader for other architecture.
> 
> Add pci_device_id table with Raven platform id and replace "is-rv"
> device property check with pci id match to support 48MHz fixed clk
> support. This enhanced flexibility to enable fixed 48MHz fch clock
> framework on other architectures by simply adding new entries into
> pci_device_id table. Also replace RV with FIXED as generic naming
> convention across all platforms.
> 
> Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
> ---
>   drivers/clk/x86/clk-fch.c | 41 ++++++++++++++++++++++++++++++---------
>   1 file changed, 32 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c
> index 8f7c5142b0f0..de556b03e184 100644
> --- a/drivers/clk/x86/clk-fch.c
> +++ b/drivers/clk/x86/clk-fch.c
> @@ -1,6 +1,6 @@
>   // SPDX-License-Identifier: MIT
>   /*
> - * clock framework for AMD Stoney based clocks
> + * clock framework for AMD FCH controller block
>    *
>    * Copyright 2018 Advanced Micro Devices, Inc.
>    */
> @@ -8,6 +8,7 @@
>   #include <linux/clk.h>
>   #include <linux/clkdev.h>
>   #include <linux/clk-provider.h>
> +#include <linux/pci.h>
>   #include <linux/platform_data/clk-fch.h>
>   #include <linux/platform_device.h>
>   
> @@ -26,22 +27,37 @@
>   #define ST_CLK_GATE	3
>   #define ST_MAX_CLKS	4
>   
> -#define RV_CLK_48M	0
> -#define RV_CLK_GATE	1
> -#define RV_MAX_CLKS	2
> +#define CLK_48M_FIXED	0
> +#define CLK_GATE_FIXED	1
> +#define CLK_MAX_FIXED	2
> +
> +/* List of supported CPU ids for fixed clk */
> +#define AMD_CPU_ID_RV			0x15D0
>   
>   static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
>   static struct clk_hw *hws[ST_MAX_CLKS];
>   
> +static const struct pci_device_id soc_pci_ids[] = {
> +	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> +	{ }
> +};
> +

Have you considered inverting it?  The number of ASICs using the "older" 
design with the mux and multiple clock sources is a fixed value, but 
we'll keep adding new ASICs in the "new" design of just 48Mhz.

Notably; I see that this series is missing the Yellow Carp ID for 
example.  We'll keep having more designs with the 48Mhz that need to be 
added to this list.


>   static int fch_clk_probe(struct platform_device *pdev)
>   {
>   	struct fch_clk_data *fch_data;
> +	struct pci_dev *rdev;
>   
>   	fch_data = dev_get_platdata(&pdev->dev);
>   	if (!fch_data || !fch_data->base)
>   		return -EINVAL;
>   
> -	if (!fch_data->is_rv) {
> +	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
> +	if (!rdev) {
> +		dev_err(&pdev->dev, "FCH device not found\n");
> +		return -ENODEV;
> +	}
> +
> +	if (!pci_match_id(soc_pci_ids, rdev)) {
>   		hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
>   			NULL, 0, 48000000);
>   		hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
> @@ -61,17 +77,18 @@ static int fch_clk_probe(struct platform_device *pdev)
>   		devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
>   			"oscout1", NULL);
>   	} else {
> -		hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
> +		hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
>   			NULL, 0, 48000000);
>   
> -		hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
> +		hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
>   			"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
>   			OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
>   
> -		devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
> +		devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
>   			"oscout1", NULL);
>   	}
>   
> +	pci_dev_put(rdev);
>   	return 0;
>   }
>   
> @@ -79,14 +96,20 @@ static int fch_clk_remove(struct platform_device *pdev)
>   {
>   	int i, clks;
>   	struct fch_clk_data *fch_data;
> +	struct pci_dev *rdev;
>   
>   	fch_data = dev_get_platdata(&pdev->dev);
>   
> -	clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
> +	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
> +	if (!rdev)
> +		return -ENODEV;
> +
> +	clks = pci_match_id(soc_pci_ids, rdev) ? CLK_MAX_FIXED : ST_MAX_CLKS;
>   
>   	for (i = 0; i < clks; i++)
>   		clk_hw_unregister(hws[i]);
>   
> +	pci_dev_put(rdev);
>   	return 0;
>   }
>   
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC
  2021-11-30 19:41   ` Limonciello, Mario
@ 2021-12-10  1:45     ` Stephen Boyd
  0 siblings, 0 replies; 9+ messages in thread
From: Stephen Boyd @ 2021-12-10  1:45 UTC (permalink / raw)
  To: Limonciello, Mario, Ajit Kumar Pandey, linux-clk, rafael
  Cc: Vijendar.Mukunda, Alexander.Deucher, Basavaraj.Hiregoudar,
	Sunil-kumar.Dommati, Michael Turquette, open list

Quoting Limonciello, Mario (2021-11-30 11:41:30)
> On 11/25/2021 05:04, Ajit Kumar Pandey wrote:
> > @@ -26,22 +27,37 @@
> >   #define ST_CLK_GATE 3
> >   #define ST_MAX_CLKS 4
> >   
> > -#define RV_CLK_48M   0
> > -#define RV_CLK_GATE  1
> > -#define RV_MAX_CLKS  2
> > +#define CLK_48M_FIXED        0
> > +#define CLK_GATE_FIXED       1
> > +#define CLK_MAX_FIXED        2
> > +
> > +/* List of supported CPU ids for fixed clk */
> > +#define AMD_CPU_ID_RV                        0x15D0
> >   
> >   static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
> >   static struct clk_hw *hws[ST_MAX_CLKS];
> >   
> > +static const struct pci_device_id soc_pci_ids[] = {
> > +     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
> > +     { }
> > +};
> > +
> 
> Have you considered inverting it?  The number of ASICs using the "older" 
> design with the mux and multiple clock sources is a fixed value, but 
> we'll keep adding new ASICs in the "new" design of just 48Mhz.
> 
> Notably; I see that this series is missing the Yellow Carp ID for 
> example.  We'll keep having more designs with the 48Mhz that need to be 
> added to this list.

+1 Let's not keep adding to a list.

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2021-12-10  1:45 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20211125110447.1188073-1-AjitKumar.Pandey@amd.com>
2021-11-25 11:04 ` [PATCH v4 1/7] x86: clk: clk-fch: Add support for newer family of AMD's SOC Ajit Kumar Pandey
2021-11-30 19:41   ` Limonciello, Mario
2021-12-10  1:45     ` Stephen Boyd
2021-11-25 11:04 ` [PATCH v4 2/7] drivers: acpi: acpi_apd: Remove unused device property "is-rv" Ajit Kumar Pandey
2021-11-25 11:04 ` [PATCH v4 3/7] ACPI: APD: Add a fmw property clk-name Ajit Kumar Pandey
2021-11-25 11:04 ` [PATCH v4 4/7] clk: x86: Use dynamic con_id string during clk registration Ajit Kumar Pandey
2021-11-25 11:04 ` [PATCH v4 5/7] clk: x86: Fix clk_gate_flags for RV_CLK_GATE Ajit Kumar Pandey
2021-11-25 11:04 ` [PATCH v4 6/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Renoir platform Ajit Kumar Pandey
2021-11-25 11:04 ` [PATCH v4 7/7] drivers: x86: clk-fch: Add 48MHz fixed clk support on Stoneyridge Ajit Kumar Pandey

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