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From: "Nícolas F. R. A. Prado" <nfraprado@collabora.com>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	srv_heupstream@mediatek.com,
	Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [v1 3/5] arm64: dts: mediatek: Correct SPI clock of MT8192
Date: Mon, 6 Dec 2021 11:47:07 -0500	[thread overview]
Message-ID: <20211206164707.u4tvsmr7fnkzs5tu@notapiano> (raw)
In-Reply-To: <20210825011120.30481-4-chun-jie.chen@mediatek.com>

Hi,

On Wed, Aug 25, 2021 at 09:11:18AM +0800, Chun-Jie Chen wrote:
> update uart0 ~ 7 clocks to the real ones.

Same comment from patch 1. But also here you had a typo: should be spi instead
of uart.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

> 
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 31d135e18784..d1c85d3e152b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -355,9 +355,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x1100a000 0 0x1000>;
>  			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI0>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -369,9 +369,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x11010000 0 0x1000>;
>  			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI1>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -383,9 +383,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x11012000 0 0x1000>;
>  			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI2>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -397,9 +397,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x11013000 0 0x1000>;
>  			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI3>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -411,9 +411,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x11018000 0 0x1000>;
>  			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI4>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -425,9 +425,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x11019000 0 0x1000>;
>  			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI5>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -439,9 +439,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x1101d000 0 0x1000>;
>  			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI6>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> @@ -453,9 +453,9 @@
>  			#size-cells = <0>;
>  			reg = <0 0x1101e000 0 0x1000>;
>  			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>,
> -				 <&clk26m>,
> -				 <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> +				 <&topckgen CLK_TOP_SPI_SEL>,
> +				 <&infracfg CLK_INFRA_SPI7>;
>  			clock-names = "parent-clk", "sel-clk", "spi-clk";
>  			status = "disabled";
>  		};
> -- 
> 2.18.0
> 
> 

  reply	other threads:[~2021-12-06 16:47 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
2021-08-25  1:11 ` [v1 1/5] arm64: dts: mediatek: Correct system timer " Chun-Jie Chen
2021-12-06 16:41   ` Nícolas F. R. A. Prado
2021-08-25  1:11 ` [v1 2/5] arm64: dts: mediatek: Correct UART " Chun-Jie Chen
2021-12-06 16:44   ` Nícolas F. R. A. Prado
2021-08-25  1:11 ` [v1 3/5] arm64: dts: mediatek: Correct SPI " Chun-Jie Chen
2021-12-06 16:47   ` Nícolas F. R. A. Prado [this message]
2021-08-25  1:11 ` [v1 4/5] arm64: dts: mediatek: Correct Nor Flash " Chun-Jie Chen
2021-12-06 16:48   ` Nícolas F. R. A. Prado
2021-08-25  1:11 ` [v1 5/5] arm64: dts: mediatek: Correct I2C " Chun-Jie Chen
2021-12-06 16:49   ` Nícolas F. R. A. Prado

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