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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Kishon Vijay Abraham I <kishon@ti.com>, bhelgaas@google.com
Cc: "Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET
Date: Tue, 8 Feb 2022 11:53:44 +0000	[thread overview]
Message-ID: <20220208115344.GB6233@lpieralisi> (raw)
In-Reply-To: <a07040ce-e043-22ac-2ee5-47a3bfdedd3b@ti.com>

On Fri, Feb 04, 2022 at 08:38:46PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
> 
> On 11/01/22 11:53 am, Kishon Vijay Abraham I wrote:
> > Hi Lorenzo,
> > 
> > On 04/01/22 9:27 pm, Lorenzo Pieralisi wrote:
> >> On Fri, Nov 26, 2021 at 02:01:18PM +0530, Kishon Vijay Abraham I wrote:
> >>> AM654 RootComplex has a hard coded 64 bit BAR of size 1MB and also has
> >>> both MSI and MSI-X capability in it's config space. If PCIEPORTBUS is
> >>> enabled, it tries to configure MSI-X and msix_mask_all() adds about 10
> >>> Second boot up delay when it tries to write to undefined location.
> >>>
> >>> Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET so that
> >>> msix_map_region() returns NULL for Root Complex and avoid un-desirable
> >>> writes to MSI-X table.
> >>
> >> I don't think this is the right fix (it is not even a fix, just a
> >> plaster to workaround an issue).
> >>
> >> What do you mean by "writing to an undefined location" ?
> >>
> >> What does "a hard coded BAR" mean ?
> >>
> >> What happens if we _rightly_ write into it (ie to size it) ?
> > 
> > There are two parts w.r.t setting the BAR; one is during the configuration and
> > the other is during the enumeration.
> > i) During the configuration, the size of the BAR is configured and the inbound
> > ATU is configured to map the BAR to a physical memory.
> > ii) During the enumeration, the size of the BAR is obtained and an address is
> > allocated and programmed in the BAR.
> > 
> > In the case of RC, for (i) above, the BAR size is configured as '0'
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-designware-host.c#n556
> > and the inbound ATU is not programmed at all.
> > 
> > However, in the case of AM654, the HW configures BAR0 for a fixed size of 1MB
> > (irrespective of what SW programmed in [i]). While this was done more for a
> > endpoint usecase, since the same IP is configured for both RC mode and EP mode,
> > the fixed BAR size is seen with RC mode as well. AM654 also has MSI-X capability
> > for RC mode (the IP should have been ideally configured to have MSI-X capability
> > for EP mode). This results in PCIEPORTBUS doing some undesired access in
> > msix_mask_all().
> > 
> > Here I configure IORESOURCE_UNSET so that memory is not allocated for RC BAR.
> 
> Do you need further clarifications on this?

There are two things here:

1) As Rob mentioned, you can write it as a quirk applying only to the
   bridge _only_
2) What you want is that the BAR should not be visible to the OS since
   it is not an actual resource. What I am questioning is whether your
   way of doing that complies with how this is done in the kernel for
   other devices/bridges. I need Bjorn's input on this since he knows
   better (especially wrt IORESOURCE_UNSET usage). I don't want to add
   any other IORESOURCE_UNSET usage that deviates from what's expected
   from it

Lorenzo

> > 
> >>
> >> Lorenzo
> >>
> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >>> ---
> >>>  drivers/pci/controller/dwc/pci-keystone.c | 8 +++++++-
> >>>  1 file changed, 7 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> >>> index 52d20fe17ee9..73e6626a0d8f 100644
> >>> --- a/drivers/pci/controller/dwc/pci-keystone.c
> >>> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> >>> @@ -557,8 +557,14 @@ static void ks_pcie_quirk(struct pci_dev *dev)
> >>>  		{ 0, },
> >>>  	};
> >>>  
> >>> -	if (pci_is_root_bus(bus))
> >>> +	if (pci_is_root_bus(bus)) {
> >>>  		bridge = dev;
> >>> +		if (pci_match_id(am6_pci_devids, bridge)) {
> >>> +			struct resource *r = &dev->resource[0];
> >>> +
> >>> +			r->flags |= IORESOURCE_UNSET;
> >>> +		}
> >>> +	}
> >>>  
> >>>  	/* look for the host bridge */
> >>>  	while (!pci_is_root_bus(bus)) {
> >>> -- 
> >>> 2.17.1
> >>>

  reply	other threads:[~2022-02-08 11:53 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-26  8:31 [PATCH v2 0/5] PCI: Keystone: Misc fixes for TI's AM65x PCIe Kishon Vijay Abraham I
2021-11-26  8:31 ` [PATCH v2 1/5] dt-bindings: PCI: ti,am65: Fix "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" to take argument Kishon Vijay Abraham I
2021-11-27 23:13   ` Rob Herring
2021-11-29  4:03     ` Kishon Vijay Abraham I
2021-12-01 22:55   ` Rob Herring
2021-11-26  8:31 ` [PATCH v2 2/5] PCI: keystone: Use phandle argument from "ti,syscon-pcie-id"/"ti,syscon-pcie-mode" Kishon Vijay Abraham I
2021-11-26  8:31 ` [PATCH v2 3/5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Kishon Vijay Abraham I
2021-11-26  8:31 ` [PATCH v2 4/5] PCI: keystone: Add quirk to mark AM654 RC BAR flag as IORESOURCE_UNSET Kishon Vijay Abraham I
2022-01-04 15:57   ` Lorenzo Pieralisi
2022-01-11  6:23     ` Kishon Vijay Abraham I
2022-02-04 15:08       ` Kishon Vijay Abraham I
2022-02-08 11:53         ` Lorenzo Pieralisi [this message]
2022-02-08 16:20           ` Bjorn Helgaas
2022-01-04 18:25   ` Rob Herring
2021-11-26  8:31 ` [PATCH v2 5/5] PCI: keystone: Set DMA mask and coherent DMA mask Kishon Vijay Abraham I
2022-02-28 11:38   ` Christian Gmeiner
2022-01-04  9:02 ` [PATCH v2 0/5] PCI: Keystone: Misc fixes for TI's AM65x PCIe Kishon Vijay Abraham I
2022-01-07 10:56 ` (subset) " Lorenzo Pieralisi

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