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From: Jon Hunter <jonathanh@nvidia.com>
To: Vidya Sagar <vidyas@nvidia.com>, <robh+dt@kernel.org>,
	<thierry.reding@gmail.com>
Cc: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <sagar.tv@gmail.com>
Subject: Re: [PATCH] arm64: tegra194: Fix Tegra194 PCIe EP compatible string
Date: Tue, 27 Jul 2021 20:05:51 +0100	[thread overview]
Message-ID: <23d08fdf-35e1-5af4-8992-17bc2f0ce7ef@nvidia.com> (raw)
In-Reply-To: <20210727185055.11010-1-vidyas@nvidia.com>


On 27/07/2021 19:50, Vidya Sagar wrote:
> The initialization sequence performed by the generic platform driver
> pcie-designware-plat.c for a DWC based implementation doesn't work for
> Tegra194. Tegra194 has a different initialization sequence requirement
> which can only be satisfied by the Tegra194 specific platform driver
> pcie-tegra194.c. So, remove the generic compatible string "snps,dw-pcie-ep"
> from Tegra194's endpoint controller nodes.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 076d5efc4c3d..2f58f3e4746b 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -2098,7 +2098,7 @@
>  	};
>  
>  	pcie_ep@14160000 {
> -		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
> +		compatible = "nvidia,tegra194-pcie-ep";
>  		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
>  		reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
>  		      <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
> @@ -2130,7 +2130,7 @@
>  	};
>  
>  	pcie_ep@14180000 {
> -		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
> +		compatible = "nvidia,tegra194-pcie-ep";
>  		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>  		reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
>  		      <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
> @@ -2162,7 +2162,7 @@
>  	};
>  
>  	pcie_ep@141a0000 {
> -		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
> +		compatible = "nvidia,tegra194-pcie-ep";
>  		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>  		reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
>  		      <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
> 


Thanks! We should also push a patch to remove this compatible string
from the example in
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt. For this
one ...

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Cheers!
Jon

-- 
nvpublic

      reply	other threads:[~2021-07-27 19:06 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 18:50 Vidya Sagar
2021-07-27 19:05 ` Jon Hunter [this message]

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