From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932336AbbCIVe0 (ORCPT ); Mon, 9 Mar 2015 17:34:26 -0400 Received: from mout.kundenserver.de ([212.227.126.131]:53187 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932219AbbCIVeW (ORCPT ); Mon, 9 Mar 2015 17:34:22 -0400 From: Arnd Bergmann To: "Grygorii.Strashko@linaro.org" Cc: Andrew Morton , linux@arm.linux.org.uk, Tejun Heo , Tony Lindgren , "linux-mm@kvack.org" , linux-arm , "linux-omap@vger.kernel.org" , Laura Abbott , open list , Santosh Shilimkar , Catalin Marinas , Peter Ujfalusi Subject: Re: ARM: OMPA4+: is it expected dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); to fail? Date: Mon, 09 Mar 2015 22:33:45 +0100 Message-ID: <2886917.pqK9QloHOD@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <54F8A68B.3080709@linaro.org> References: <54F8A68B.3080709@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:fQY5//LhRNtGKkQlJkvStCjYm4cX1W1nhSkWH2CL5muvfWKV6JX ZNzIyiL/f4bhLX30OH1L+Y5bmSr2H579nHnW+Nxo2RoEUG+pK6xnraxgyLVMqF4S9ta7KQi GoVuygQNcd/n31mqvhnbjcC1ir8UzrSHeXjVDF4ULrcEaEoyVa4jhWYHbxecWWvO8IE4bzF mILxiSYJGxToI9W3DlwLA== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 05 March 2015 20:55:07 Grygorii.Strashko@linaro.org wrote: > Hi All, > > Now I can see very interesting behavior related to dma_coerce_mask_and_coherent() > and friends which I'd like to explain and clarify. > > Below is set of questions I have (why - I explained below): > - Is expected dma_coerce_mask_and_coherent(DMA_BIT_MASK(64)) and friends to fail on 32 bits HW? No. dma_coerce_mask_and_coherent() is meant to ignore the actual mask. It's usually considered a bug to use this function for that reason. > - What is expected value for max_pfn: max_phys_pfn or max_phys_pfn + 1? > > - What is expected value for struct memblock_region->size: mem_range_size or mem_range_size - 1? > > - What is expected value to be returned by memblock_end_of_DRAM(): > @base + @size(max_phys_addr + 1) or @base + @size - 1(max_phys_addr)? > > > I'm working with BeaglBoard-X15 (AM572x/DRA7xx) board and have following code in OMAP ASOC driver > which is failed SOMETIMES during the boot with error -EIO. > === to omap-pcm.c: > omap_pcm_new() { > ... > ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(64)); > ^^ failed sometimes > if (ret) > return ret; > } The code should be fixed to use dma_set_mask_and_coherent(), which is expected to fail if the bus is incapable of addressing all RAM within the mask. > I'd be very appreciated for any comments/clarification on questions I've listed at the > beginning of my e-mail - there are no patches from my side as I'd like to understand > expected behavior of the kernel first (especially taking into account that any > memblock changes might affect on at least half of arches). Is the device you have actually 64-bit capable? Is the bus it is connected to 64-bit wide? Does the dma-ranges property of the parent bus reflect the correct address width? Arnd