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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode
Date: Mon, 2 Aug 2021 13:14:13 +0530 [thread overview]
Message-ID: <4011d566-1a5b-51a3-dcee-09f60af0a7bb@arm.com> (raw)
In-Reply-To: <20210728135217.591173-8-suzuki.poulose@arm.com>
On 7/28/21 7:22 PM, Suzuki K Poulose wrote:
> Arm Neoverse-N2 and the Cortex-A710 cores are affected
> by a CPU erratum where the TRBE will overwrite the trace buffer
> in FILL mode. The TRBE doesn't stop (as expected in FILL mode)
> when it reaches the limit and wraps to the base to continue
> writing upto 3 cache lines. This will overwrite any trace that
> was written previously.
>
> Add the Neoverse-N2 erratumi(#2139208) and Cortex-A710 erratum
Small nit. Stray 'i' here ^^^^
> (#2119858) to the detection logic.
>
> This will be used by the TRBE driver in later patches to work
> around the issue. The detection has been kept with the core
> arm64 errata framework list to make sure :
> - We don't duplicate the framework in TRBE driver
> - The errata detection is advertised like the rest
> of the CPU errata.
>
> Note that the Kconfig entries will be added after we have added
> the work around in the TRBE driver, which depends on the cpucap
> from here.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> cc: Leo Yan <leo.yan@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/kernel/cpu_errata.c | 25 +++++++++++++++++++++++++
> arch/arm64/tools/cpucaps | 1 +
> 2 files changed, 26 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index e2c20c036442..ccd757373f36 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -340,6 +340,18 @@ static const struct midr_range erratum_1463225[] = {
> };
> #endif
>
> +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> +static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> +#ifdef CONFIG_ARM64_ERRATUM_2139208
> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> +#endif
> +#ifdef CONFIG_ARM64_ERRATUM_2119858
> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> +#endif
> + {},
> +};
> +#endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
> +
> const struct arm64_cpu_capabilities arm64_errata[] = {
> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
> {
> @@ -533,6 +545,19 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
> ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
> },
> +#endif
> +#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> + {
> + /*
> + * The erratum work around is handled within the TRBE
> + * driver and can be applied per-cpu. So, we can allow
> + * a late CPU to come online with this erratum.
> + */
> + .desc = "ARM erratum 2119858 or 2139208",
> + .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
> + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> + CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
> + },
> #endif
> {
> }
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 49305c2e6dfd..1ccb92165bd8 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -53,6 +53,7 @@ WORKAROUND_1418040
> WORKAROUND_1463225
> WORKAROUND_1508412
> WORKAROUND_1542419
> +WORKAROUND_TRBE_OVERWRITE_FILL_MODE
> WORKAROUND_CAVIUM_23154
> WORKAROUND_CAVIUM_27456
> WORKAROUND_CAVIUM_30115
>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
next prev parent reply other threads:[~2021-08-02 7:43 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-28 13:52 [PATCH 00/10] arm64: Self-hosted trace related erratum workarouds Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-08-02 6:43 ` Anshuman Khandual
2021-09-07 9:04 ` Suzuki K Poulose
2021-09-09 2:55 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 02/10] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-07-30 10:01 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 03/10] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-07-30 10:05 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 04/10] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-07-30 10:53 ` Anshuman Khandual
2021-07-28 13:52 ` [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-07-30 11:02 ` Anshuman Khandual
2021-07-30 14:29 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-07-30 11:26 ` Anshuman Khandual
2021-07-30 14:31 ` Suzuki K Poulose
2021-08-02 11:21 ` Catalin Marinas
2021-08-02 11:21 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 07/10] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-08-02 7:44 ` Anshuman Khandual [this message]
2021-08-02 11:22 ` Catalin Marinas
2021-08-06 12:44 ` Linu Cherian
2021-09-07 9:10 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 08/10] coresight: trbe: Workaround TRBE errat " Suzuki K Poulose
2021-08-03 10:25 ` Anshuman Khandual
2021-09-07 9:58 ` Suzuki K Poulose
2021-09-09 4:21 ` Anshuman Khandual
2021-09-09 8:37 ` Suzuki K Poulose
2021-08-06 16:09 ` Linu Cherian
2021-09-07 9:18 ` Suzuki K Poulose
2021-07-28 13:52 ` [PATCH 09/10] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-08-02 9:34 ` Anshuman Khandual
2021-08-02 11:24 ` Catalin Marinas
2021-07-28 13:52 ` [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-07-29 9:55 ` Marc Zyngier
2021-07-29 10:41 ` Suzuki K Poulose
2021-08-02 9:12 ` Anshuman Khandual
2021-08-02 9:35 ` Marc Zyngier
2021-08-03 3:51 ` Anshuman Khandual
2021-09-08 13:39 ` Suzuki K Poulose
2021-08-02 11:27 ` Catalin Marinas
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