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Mon, 16 Aug 2021 02:45:26 -0700 (PDT) Received: from [192.168.8.102] ([86.32.42.198]) by smtp.gmail.com with ESMTPSA id wc16sm3479626ejb.15.2021.08.16.02.45.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Aug 2021 02:45:26 -0700 (PDT) Subject: Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support To: Sam Protsenko Cc: Sylwester Nawrocki , =?UTF-8?Q?Pawe=c5=82_Chmiel?= , Chanwoo Choi , Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" References: <20210811114827.27322-1-semen.protsenko@linaro.org> <20210811114827.27322-8-semen.protsenko@linaro.org> From: Krzysztof Kozlowski Message-ID: <40dd9a0a-eccc-1b0c-70ec-06edc8b91177@canonical.com> Date: Mon, 16 Aug 2021 11:45:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/08/2021 19:42, Sam Protsenko wrote: > On Thu, 12 Aug 2021 at 11:17, Krzysztof Kozlowski > wrote: >> >> On 11/08/2021 13:48, Sam Protsenko wrote: >>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC. >>> >>> This patch adds minimal SoC support by including next Device Tree nodes: >>> >>> 1. Octa cores (Cortex-A55), supporting PSCI v1.0 >>> 2. ARM architecture timer (armv8-timer) >>> 3. Interrupt controller (GIC-400) >>> 4. Pinctrl nodes for GPIO >>> 5. Serial node >>> >>> Signed-off-by: Sam Protsenko >>> --- >>> Changes in v3: >>> - Used generic fixed clock for serial >>> >>> Changes in v2: >>> * Commit message: >>> - Documented added dts features instead of CPU features >>> >>> * exynos850-usi.dtsi: >>> - Removed, moved everything to exynos850.dtsi >>> >>> * exynos850.dtsi: >>> - Root node: >>> - Added comment about engineering name (Exynos3830) >>> - Renamed pinctrl nodes, adding domain names >>> - Used hard coded IRQ numbers instead of named constants everywhere >>> - Added soc node, moved next nodes there: gic, clock, pinctrls and >>> serial >>> - Used address-cells=1 for soc node and removed unneeded 0x0 from >>> reg properties >>> - Moved exynos850-pinctrl.dtsi include line to the end of >>> exynos850.dtsi >>> - Coding style fixes >>> - cpus: >>> - Used address-cells=1 for cpus node >>> - Renamed cpu@0001 to cpu@1, and so on >>> - Left only "arm,cortex-a55" for cpus compatible >>> - Renamed reg = <0x0001> to <0x1> for cpus >>> - armv8 timer: >>> - Add comment about missing HV timer IRQ to armv8 timer node >>> - Removed not existing properties from armv8 timer node >>> - Fixed cpu number in CPU_MASK() >>> - Removed obsolete clock-frequency property >>> - GIC: >>> - Fixed GIC type to be GIC-400 >>> - Fixed size of GIC's 2nd region to be 0x2000 >>> - serial node: >>> - Hard coded clock number for serial_0 for now; will replace with >>> named const once proper clock driver is implemented >>> - Removed gate_uart_clk0 clock from serial_0, as that clock is not >>> supported in serial driver anyway (yet) >>> - clock node: >>> - Fixed clock controller node name (@0x12.. -> @12..) >>> >>> * exynos850-pinctrl.dtsi: >>> - Referenced pinctrl nodes instead of defining those again in root node >>> - Fixed interrupt-cells (3 -> 2) >>> - Fixed USI related comments for pin config nodes >>> - Removed decon_f_te_* and fm_lna_en nodes (won't be used) >>> - Reordered pin config nodes by pin numbers >>> - Improved all comments >>> - Used existing named constants for pin-function and pin-pud >>> - Fixed node names (used hyphens instead of underscore) >>> - Fixed warnings found in W=1 build >>> >>> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++ >>> 2 files changed, 1009 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> new file mode 100644 >>> index 000000000000..ba5d5f33e2f6 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi >>> @@ -0,0 +1,748 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source >>> + * >>> + * Copyright (C) 2017 Samsung Electronics Co., Ltd. >>> + * Copyright (C) 2021 Linaro Ltd. >>> + * >>> + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device >>> + * tree nodes in this file. >>> + */ >>> + >>> +#include >>> +#include >>> + >>> +&pinctrl_alive { >>> + gpa0: gpa0 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> + gpa1: gpa1 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> + gpa2: gpa2 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> + gpa3: gpa3 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> + gpa4: gpa4 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + ; >>> + }; >>> + >>> + gpq0: gpq0 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + }; >>> + >>> + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ >>> + i2c5_bus: i2c5-bus { >>> + samsung,pins = "gpa3-5", "gpa3-6"; >>> + samsung,pin-function = ; >>> + samsung,pin-pud = ; >>> + samsung,pin-drv = <0>; >>> + }; >>> + >>> + /* I2C6 (also called MOTOR_I2C in TRM) */ >>> + i2c6_bus: i2c6-bus { >>> + samsung,pins = "gpa3-7", "gpa4-0"; >>> + samsung,pin-function = ; >>> + samsung,pin-pud = ; >>> + samsung,pin-drv = <0>; >>> + }; >>> + >>> + /* USI: UART */ >>> + uart0_bus: uart0-bus { >>> + samsung,pins = "gpq0-0", "gpq0-1"; >>> + samsung,pin-function = ; >>> + samsung,pin-pud = ; >>> + }; >>> +}; >>> + >>> +&pinctrl_cmgp { >>> + gpm0: gpm0 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + gpm1: gpm1 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + gpm2: gpm2 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + gpm3: gpm3 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + gpm4: gpm4 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + gpm5: gpm5 { >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&gic>; >>> + interrupts = ; >>> + }; >>> + >>> + /* USI_CMGP0: HSI2C function */ >>> + hsi2c3_bus: hsi2c3-bus { >>> + samsung,pins = "gpm0-0", "gpm1-0"; >>> + samsung,pin-function = ; >>> + samsung,pin-pud = ; >>> + samsung,pin-drv = <0>; >> >> There are also macros for DRV. >> > > Unfortunately, existing DRV macros won't work for Exynos850. DRV > constants have different meaning for different GPIO domains in > Exynos850, so I thought introducing several groups of DRV constants > might be confusing. But please let me know if you still want me do > that. > Oh, damn, raw values are ok then. Best regards, Krzysztof