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From: "H. Peter Anvin" <>
To: Mikael Pettersson <>
Subject: Re: Support for i386 PATs
Date: Sat, 27 Jan 2007 23:54:08 -0800	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Mikael Pettersson wrote:
> 3) Many Intel processors, including at least most P6s and probably
> also some P4s, have an erratum which effectively halves the number
> of available PAT entries, forcing an OS to make the low 4 and upper
> 4 PAT entries identical.
> I don't know if 4 PAT types suffice for the kinds of uses people
> have in mind. But support for PAT would either have to restrict
> itself to only 4 PAT types, or ensure that it is only enabled on
> new enough processors where it actually works.
> You will need to read all available Intel errata sheets (spec updates)
> to determine which processors are affected and which are OK.

There aren't really that many useful caching types, so it probably 
doesn't matter all that much.

The types that matters most are WB, WC, and UC.  The fourth one could be 
WT, or it could be UC- (however, UC- can *always* be emulated by simply 
having the kernel being aware of the MTRR settings.)


  reply	other threads:[~2007-01-28  7:54 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-01-27 10:59 Mikael Pettersson
2007-01-28  7:54 ` H. Peter Anvin [this message]
  -- strict thread matches above, loose matches on Subject: below --
2007-01-27  9:20 Thomas Hellström
2007-01-27  9:33 ` Avi Kivity
2007-01-28 21:48 ` Dave Jones
2007-01-30 15:50   ` Thomas Hellström

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