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From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Vince Weaver <vincent.weaver@maine.edu>
Cc: linux-kernel@vger.kernel.org, Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	"Liang, Kan" <kan.liang@intel.com>
Subject: Re: [perf] fuzzer triggers unchecked MSR access error: WRMSR to 0x318
Date: Thu, 29 Jul 2021 09:21:01 -0400	[thread overview]
Message-ID: <45bee582-0f89-5125-82e7-92caf8b741ea@linux.intel.com> (raw)
In-Reply-To: <YQJxka3dxgdIdebG@hirez.programming.kicks-ass.net>



On 7/29/2021 5:14 AM, Peter Zijlstra wrote:
> On Wed, Jul 28, 2021 at 12:49:43PM -0400, Vince Weaver wrote:
>> [32694.087403] unchecked MSR access error: WRMSR to 0x318 (tried to write 0x0000000000000000) at rIP: 0xffffffff8106f854 (native_write_msr+0x4/0x20)
>> [32694.101374] Call Trace:
>> [32694.103974]  perf_clear_dirty_counters+0x86/0x100
> 
> Hmm.. if I read this right that's MSR_ARCH_PERFMON_FIXED_CTR0 + i, given
> that FIXED_CTR0 is 0x309 that gives i == 15, which is FIXED_BTS.
> 
> I'm thinking something like this ought to cure things.
> 
> ---
>   arch/x86/events/core.c | 12 +++++++-----
>   1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index 1eb45139fcc6..04edf8017961 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -2489,13 +2489,15 @@ void perf_clear_dirty_counters(void)
>   		return;
>   
>   	for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
> -		/* Metrics and fake events don't have corresponding HW counters. */
> -		if (is_metric_idx(i) || (i == INTEL_PMC_IDX_FIXED_VLBR))
> -			continue;
> -		else if (i >= INTEL_PMC_IDX_FIXED)
> +		if (i >= INTEL_PMC_IDX_FIXED) {
> +			/* Metrics and fake events don't have corresponding HW counters. */
> +			if ((i - INTEL_PMC_IDX_FIXED) >= x86_pmu.num_counters_fixed)

Yes, the fix is better. My previous implementation tries to pick up all 
the special cases. It's very likely to miss some special cases like 
FIXED_BTS and probably any new fake events added later if there are.
Thanks for the fix.

The x86_pmu.num_counters_fixed should work well on HSW. But we have 
hybrid machines now. I think we can use
hybrid(cpuc->pmu, num_counters_fixed) instead, which should be more 
accurate.


Thanks,
Kan

> +				continue;
> +
>   			wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
> -		else
> +		} else {
>   			wrmsrl(x86_pmu_event_addr(i), 0);
> +		}
>   	}
>   
>   	bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
> 

  reply	other threads:[~2021-07-29 13:21 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-28 16:49 Vince Weaver
2021-07-29  9:14 ` Peter Zijlstra
2021-07-29 13:21   ` Liang, Kan [this message]
2021-07-29 15:30     ` Peter Zijlstra
2021-08-02 11:40       ` Like Xu
2021-07-29 16:54   ` Vince Weaver
2021-08-05  9:34   ` [tip: perf/urgent] perf/x86: Fix out of bound MSR access tip-bot2 for Peter Zijlstra

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