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From: "Jan Beulich" <JBeulich@novell.com>
To: <mingo@elte.hu>, <tglx@linutronix.de>, <hpa@zytor.com>
Cc: <linux-kernel@vger.kernel.org>
Subject: [PATCH] x86: adjust section placement in AMD northbridge related code
Date: Wed, 09 Feb 2011 08:26:53 +0000 [thread overview]
Message-ID: <4D525DDD0200007800030F07@vpn.id2.novell.com> (raw)
amd_nb_misc_ids[] can live in .rodata, and enable_pci_io_ecs() can be
moved into .cpuinit.text.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
---
arch/x86/include/asm/amd_nb.h | 2 +-
arch/x86/kernel/amd_nb.c | 7 ++++---
arch/x86/pci/amd_bus.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)
--- 2.6.38-rc4/arch/x86/include/asm/amd_nb.h
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/include/asm/amd_nb.h
@@ -9,7 +9,7 @@ struct amd_nb_bus_dev_range {
u8 dev_limit;
};
-extern struct pci_device_id amd_nb_misc_ids[];
+extern const struct pci_device_id amd_nb_misc_ids[];
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
struct bootnode;
--- 2.6.38-rc4/arch/x86/kernel/amd_nb.c
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/kernel/amd_nb.c
@@ -12,7 +12,7 @@
static u32 *flush_words;
-struct pci_device_id amd_nb_misc_ids[] = {
+const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
@@ -31,7 +31,7 @@ struct amd_northbridge_info amd_northbri
EXPORT_SYMBOL(amd_northbridges);
static struct pci_dev *next_northbridge(struct pci_dev *dev,
- struct pci_device_id *ids)
+ const struct pci_device_id *ids)
{
do {
dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
@@ -93,8 +93,9 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges
they're useless anyways */
int __init early_is_amd_nb(u32 device)
{
- struct pci_device_id *id;
+ const struct pci_device_id *id;
u32 vendor = device & 0xffff;
+
device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device)
--- 2.6.38-rc4/arch/x86/pci/amd_bus.c
+++ 2.6.38-rc4-x86-amd-nb-sections/arch/x86/pci/amd_bus.c
@@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info
#define ENABLE_CF8_EXT_CFG (1ULL << 46)
-static void enable_pci_io_ecs(void *unused)
+static void __cpuinit enable_pci_io_ecs(void *unused)
{
u64 reg;
rdmsrl(MSR_AMD64_NB_CFG, reg);
next reply other threads:[~2011-02-09 8:26 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-09 8:26 Jan Beulich [this message]
2011-02-10 14:44 ` [tip:x86/amd-nb] x86: Adjust " tip-bot for Jan Beulich
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