From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751399AbeEBMfk (ORCPT ); Wed, 2 May 2018 08:35:40 -0400 Received: from mo4-p01-ob.smtp.rzone.de ([81.169.146.164]:34682 "EHLO mo4-p01-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750930AbeEBMfh (ORCPT ); Wed, 2 May 2018 08:35:37 -0400 X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBj4Qpw87WisNN2EzqY" X-RZG-CLASS-ID: mo00 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Subject: Re: [PATCH v5 5/7] gpio: pca953x: fix address calculation for pcal6524 From: "H. Nikolaus Schaller" In-Reply-To: Date: Wed, 2 May 2018 14:35:24 +0200 Cc: Kumar Gala , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Linus Walleij , Alexandre Courbot , devicetree , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Discussions about the Letux Kernel , kernel@pyra-handheld.com Message-Id: <4F016FCD-04B0-4EE1-A9F4-5A182DD437EF@goldelico.com> References: To: Andy Shevchenko X-Mailer: Apple Mail (2.3124) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w42CZk40014145 Hi Andy, > Am 02.05.2018 um 14:28 schrieb Andy Shevchenko : > > On Sat, Apr 28, 2018 at 7:31 PM, H. Nikolaus Schaller wrote: >> The register constants are so far defined in a way that they fit >> for the pcal9555a when shifted by the number of banks, i.e. are >> multiplied by 2 in the accessor function. >> >> Now, the pcal6524 has 3 banks which means the relative offset >> is multiplied by 4 for the standard registers. >> >> Simply applying the bit shift to the extended registers gives >> a wrong result, since the base offset is already included in >> the offset. >> >> Therefore, we add code to the 24 bit accessor functions to >> adjust the register number for these exended registers. >> > > Suggested-by ? Detecting that we need to adjust the registers generally was from me, but your suggestion of an improved formula should of course be mentioned and appreciated! I'll think about a good formulation for v6. BR and thanks, Nikolaus > >> Signed-off-by: H. Nikolaus Schaller >> --- >> drivers/gpio/gpio-pca953x.c | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c >> index fc863faa3ce4..4194495a7990 100644 >> --- a/drivers/gpio/gpio-pca953x.c >> +++ b/drivers/gpio/gpio-pca953x.c >> @@ -221,9 +221,11 @@ static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) >> static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) >> { >> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); >> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; >> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; >> >> return i2c_smbus_write_i2c_block_data(chip->client, >> - (reg << bank_shift) | REG_ADDR_AI, >> + pinctrl | addr | REG_ADDR_AI, >> NBANK(chip), val); >> } >> >> @@ -263,9 +265,11 @@ static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) >> static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) >> { >> int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); >> + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; >> + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; >> >> return i2c_smbus_read_i2c_block_data(chip->client, >> - (reg << bank_shift) | REG_ADDR_AI, >> + pinctrl | addr | REG_ADDR_AI, >> NBANK(chip), val); >> } >> >> -- >> 2.12.2 >> > > > > -- > With Best Regards, > Andy Shevchenko