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From: Lucas tanure <tanureal@opensource.cirrus.com>
To: Mark Brown <broonie@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Sanjay R Mehta <sanju.mehta@amd.com>,
	Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@amd.com>,
	<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
	<patches@opensource.cirrus.com>
Subject: Re: [PATCH 3/9] regmap: spi: SPI_CONTROLLER_CS_PER_TRANSFER affects max read/write
Date: Wed, 25 Aug 2021 18:13:01 +0100	[thread overview]
Message-ID: <4c604d13-f177-ff75-d21f-27613e1b763f@opensource.cirrus.com> (raw)
In-Reply-To: <20210824163721.GF4393@sirena.org.uk>

On 8/24/21 5:37 PM, Mark Brown wrote:
> On Tue, Aug 24, 2021 at 11:40:35AM +0100, Lucas Tanure wrote:
>> regmap-spi will split data and address between two transfers in the
>> same message so use addr_affects_max_raw_rw to flag that the number
>> bytes to read or write should be a little less (address + padding size),
>> so that the SPI controller can merge the entire message into a single
>> CS period
> 
> This should be handled by the SPI core, it's already relying on being
> able to do multiple transfers to handle message size limits and in any
> case this is a super standard thing to do so many clients would require
> special code.  The core should transparently coalesce things where it
> can, or error out if it can't, like it currently does when splitting
> transfers up.
> 
__spi_validate seems a good candidate, but I don't think spi have enough
information to merge two transfers into a single one.

For a message with N transfers how can spi core decide what to merge or 
what not merge. If mergers everything and is less than max_transfer_size 
success, but if bigger will need to stop merging and add an address in 
front of the next not merged transfer, but spi core is not aware of 
addresses
And in the case of multiple addresses and data transfers, how it will 
know doesn't need to be merged?

For me seems more reasonable for the regmap-spi stop splitting address
and data. Or at least if the controller has some flag change the bus for
one where it uses different functions for gather_write, async_write etc

Can you point which way you think the code should go? Investigate more 
spi core to coalesce transfers or change regmap-spi to not split address 
and data anymore?

Thanks
Lucas

  reply	other threads:[~2021-08-25 17:13 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-24 10:40 [PATCH 0/9] Improve support for AMD SPI controllers Lucas Tanure
2021-08-24 10:40 ` [PATCH 1/9] regmap: spi: Set regmap max raw r/w from max_transfer_size Lucas Tanure
2021-08-24 16:42   ` Mark Brown
2021-08-24 10:40 ` [PATCH 2/9] spi: core: Add flag for controllers that can't hold cs between transfers Lucas Tanure
2021-08-24 16:38   ` Mark Brown
2021-08-24 10:40 ` [PATCH 3/9] regmap: spi: SPI_CONTROLLER_CS_PER_TRANSFER affects max read/write Lucas Tanure
2021-08-24 16:37   ` Mark Brown
2021-08-25 17:13     ` Lucas tanure [this message]
2021-08-25 17:21       ` Mark Brown
2021-08-24 10:40 ` [PATCH 4/9] spi: amd: Refactor code to use less spi_master_get_devdata Lucas Tanure
2021-08-24 10:40 ` [PATCH 5/9] spi: amd: Refactor amd_spi_busy_wait to use readl_poll_timeout Lucas Tanure
2021-08-24 16:46   ` Mark Brown
2021-08-24 10:40 ` [PATCH 6/9] spi: amd: Remove uneeded variable Lucas Tanure
2021-08-24 10:40 ` [PATCH 7/9] spi: amd: Check for idle bus before execute opcode Lucas Tanure
2021-08-24 16:49   ` Mark Brown
2021-08-24 10:40 ` [PATCH 8/9] spi: amd: Refactor to overcome 70 bytes per CS limitation Lucas Tanure
2021-08-24 17:16   ` Mark Brown
2021-08-24 17:18     ` Mark Brown
2021-08-24 10:40 ` [PATCH 9/9] spi: amd: Add support for latest platform Lucas Tanure
2021-08-24 15:44   ` kernel test robot
2021-08-24 17:19   ` Mark Brown

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