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From: "H. Peter Anvin" <h.peter.anvin@intel.com>
To: Ross Zwisler <ross.zwisler@linux.intel.com>,
	linux-kernel@vger.kernel.org
Cc: Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH v3 1/2] x86: Add support for the pcommit instruction
Date: Wed, 11 Feb 2015 14:24:02 -0800	[thread overview]
Message-ID: <54DBD682.3000306@intel.com> (raw)
In-Reply-To: <1422377631-8986-2-git-send-email-ross.zwisler@linux.intel.com>

On 01/27/2015 08:53 AM, Ross Zwisler wrote:
> Add support for the new pcommit (persistent commit) instruction.  This
> instruction was announced in the document "Intel Architecture
> Instruction Set Extensions Programming Reference" with reference number
> 319433-022.
> 
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
> 
> The pcommit instruction ensures that data that has been flushed from the
> processor's cache hierarchy with clwb, clflushopt or clflush is accepted to
> memory and is durable on the DIMM.  The primary use case for this is persistent
> memory.
> 
> This function shows how to properly use clwb/clflushopt/clflush and
> pcommit with appropriate fencing:
> 
> void flush_and_commit_buffer(void *vaddr, unsigned int size)
> {
> 	void *vend = vaddr + size - 1;
> 
> 	for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
> 		clwb(vaddr);
> 
> 	/* Flush any possible final partial cacheline */
> 	clwb(vend);
> 
> 	/*
> 	 * sfence to order clwb/clflushopt/clflush cache flushes
> 	 * mfence via mb() also works
> 	 */
> 	wmb();
> 
> 	/* pcommit and the required sfence for ordering */
> 	pcommit_sfence();
> }
> 
> After this function completes the data pointed to by vaddr is has been
> accepted to memory and will be durable if the vaddr points to
> persistent memory.
> 
> Pcommit must always be ordered by an mfence or sfence, so to help
> simplify things we include both the pcommit and the required sfence in
> the alternatives generated by pcommit_sfence().  The other option is to
> keep them separated, but on platforms that don't support pcommit this
> would then turn into:
> 
> void flush_and_commit_buffer(void *vaddr, unsigned int size)
> {
>         void *vend = vaddr + size - 1;
> 
>         for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
>                 clwb(vaddr);
> 
>         /* Flush any possible final partial cacheline */
>         clwb(vend);
> 
>         /*
>          * sfence to order clwb/clflushopt/clflush cache flushes
>          * mfence via mb() also works
>          */
>         wmb();
> 
>         nop(); /* from pcommit(), via alternatives */
> 
>         /*
>          * sfence to order pcommit
>          * mfence via mb() also works
>          */
>         wmb();
> }
> 
> This is still correct, but now you've got two fences separated by only a
> nop.  With the commit and the fence together in pcommit_sfence() you
> avoid the final unneeded fence.

Acked-by: H. Peter Anvin <hpa@linux.intel.com>



  parent reply	other threads:[~2015-02-11 22:24 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-27 16:53 [PATCH v3 0/2] add support for new persistent memory instructions Ross Zwisler
2015-01-27 16:53 ` [PATCH v3 1/2] x86: Add support for the pcommit instruction Ross Zwisler
2015-01-28 10:58   ` Borislav Petkov
2015-01-28 17:10   ` Elliott, Robert (Server Storage)
2015-01-28 17:21     ` Borislav Petkov
2015-01-28 17:27       ` Ross Zwisler
2015-02-11 22:24   ` H. Peter Anvin [this message]
2015-02-19  0:29   ` [tip:x86/asm] " tip-bot for Ross Zwisler
2015-02-19  1:15     ` Ingo Molnar
2015-02-19 17:21       ` Ross Zwisler
2015-02-19 17:33         ` Borislav Petkov
2015-02-19 17:41           ` Ross Zwisler
2015-01-27 16:53 ` [PATCH v3 2/2] x86: Add support for the clwb instruction Ross Zwisler
2015-01-28 10:58   ` Borislav Petkov
2015-02-11 22:25   ` H. Peter Anvin
2015-02-19  0:29   ` [tip:x86/asm] " tip-bot for Ross Zwisler
2015-04-02 20:31     ` Ross Zwisler
2015-04-03  5:04       ` Ingo Molnar
2015-04-03  5:10   ` [tip:x86/asm] x86/asm: Add support for the CLWB instruction tip-bot for Ross Zwisler
2015-02-05 16:24 ` [PATCH v3 0/2] add support for new persistent memory instructions Ross Zwisler

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