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From: Markos Chandras <>
To: David Daney <>, <>,
Cc: <>,
	Leonid Yegoshin <>,
	David Daney <>
Subject: Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction"
Date: Wed, 11 Mar 2015 08:28:55 +0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 02/23/2015 10:52 PM, David Daney wrote:
> From: David Daney <>
> This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
> There are two problems:
> 1) It breaks OCTEON, which will now crash in early boot with:
>   Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
> 2) The logic is broken.
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
> is required.  The offending patch attempts (and fails) to change the
> meaning to be that EHB is part of the ISA.
> Signed-off-by: David Daney <>
> ---

First of all sorry about the octeon breakage.

However, whilst this patch will fix Octeon it will break R6

Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?


  parent reply	other threads:[~2015-03-11  8:29 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-23 22:52 David Daney
2015-02-24  1:10 ` Maciej W. Rozycki
2015-03-11  8:28 ` Markos Chandras [this message]
2015-03-11 16:51   ` David Daney

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