From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752332AbbCOTGc (ORCPT ); Sun, 15 Mar 2015 15:06:32 -0400 Received: from mail-la0-f43.google.com ([209.85.215.43]:34479 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751249AbbCOTG3 (ORCPT ); Sun, 15 Mar 2015 15:06:29 -0400 Message-ID: <5505D823.7020501@gmail.com> Date: Sun, 15 Mar 2015 22:06:11 +0300 From: Dmitry Osipenko User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Thierry Reding , Russell King , linux-tegra@vger.kernel.org, Ben Dooks , linux-arm-kernel@lists.infradead.org, Bob Mottram , linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] ARM: l2c: Maintain CPU endianness for early resume function References: <1421757420-20983-1-git-send-email-digetx@gmail.com> <20150311101845.GL19577@ulmo.nvidia.com> In-Reply-To: <20150311101845.GL19577@ulmo.nvidia.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 11.03.2015 13:18, Thierry Reding пишет: > On Tue, Jan 20, 2015 at 03:36:55PM +0300, Dmitry Osipenko wrote: >> In big endian CPU mode l2x0_saved_regs structure stores registers values in BE >> format. In order to maintain BE CPU mode, these values and immediate constants >> must be converted back to LE format before writing them to cache controller. >> >> Signed-off-by: Dmitry Osipenko >> --- >> arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++ >> 1 file changed, 10 insertions(+) > > Hi Russell, > > Did you get a chance yet to review this patch? It's a dependency for > enabling big-endian support on Tegra. As such, I wonder if you would be > willing to ack it, so that I can take it through the Tegra tree along > with the rest of the patches. > > If you prefer to take it through the ARM tree, that's fine, too. In that > case would you be able to provide a stable branch that I can merge into > the Tegra tree to resolve the dependency? > > Thanks, > Thierry > >> diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S >> index fda415e..9f99c7e 100644 >> --- a/arch/arm/mm/l2c-l2x0-resume.S >> +++ b/arch/arm/mm/l2c-l2x0-resume.S >> @@ -30,6 +30,15 @@ ENTRY(l2c310_early_resume) >> teq r1, #0 >> reteq lr >> >> + @ Reverse for big endian kernel >> +ARM_BE8(rev r2, r2) >> +ARM_BE8(rev r3, r3) >> +ARM_BE8(rev r4, r4) >> +ARM_BE8(rev r5, r5) >> +ARM_BE8(rev r6, r6) >> +ARM_BE8(rev r7, r7) >> +ARM_BE8(rev r8, r8) >> + >> @ The prefetch and power control registers are revision dependent >> @ and can be written whether or not the L2 cache is enabled >> ldr r0, [r1, #L2X0_CACHE_ID] >> @@ -51,6 +60,7 @@ ENTRY(l2c310_early_resume) >> >> str r2, [r1, #L2X0_AUX_CTRL] >> mov r9, #L2X0_CTRL_EN >> +ARM_BE8(rev r9, r9) >> str r9, [r1, #L2X0_CTRL] >> ret lr >> ENDPROC(l2c310_early_resume) >> -- >> 2.2.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel This patch missed register reverse for "ldr". Please hold it, I'll send v3. -- Dmitry