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From: "Chuanjia Liu (柳传嘉)" <Chuanjia.Liu@mediatek.com>
To: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"helgaas@kernel.org" <helgaas@kernel.org>
Cc: "linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"frank-w@public-files.de" <frank-w@public-files.de>,
	"Yong Wu (吴勇)" <Yong.Wu@mediatek.com>,
	"Jianjun Wang (王建军)" <Jianjun.Wang@mediatek.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"Ryder Lee (李庚諺)" <Ryder.Lee@mediatek.com>
Subject: Re: [PATCH v11 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base address and parse node
Date: Tue, 17 Aug 2021 11:18:54 +0000	[thread overview]
Message-ID: <55495cac6a6f7bd3efc2e2932a2a4b4a76789e94.camel@mediatek.com> (raw)
In-Reply-To: <20210813152239.GA15515@lpieralisi>

On Fri, 2021-08-13 at 16:22 +0100, Lorenzo Pieralisi wrote:
> On Tue, Aug 10, 2021 at 02:42:50PM -0500, Bjorn Helgaas wrote:
> > On Mon, Jul 19, 2021 at 03:34:54PM +0800, Chuanjia Liu wrote:
> > > For the new dts format, add a new method to get
> > > shared pcie-cfg base address and parse node.
> > 
> > This commit log doesn't seem to really cover what's going on
> > here.  It
> > looks like:
> > 
> >   - You added a check for "mediatek,generic-pciecfg" (I guess this
> > is
> >     the "shared pcie-cfg base address" part).  Probably could have
> >     been its own patch.
> > 
> >   - You added checks for "interrupt-names" and "pcie_irq".  Not
> >     explained in commit log; probably could have been its own
> > patch,
> >     too.
> > 
> >   - You now look for "linux,pci-domain" (via
> > of_get_pci_domain_nr()).
> >     If present, you parse only one port instead of looking for all
> > the
> >     children of the node.
> > 
> >     That's sort of weird behavior -- why should the presence of
> >     "linux,pci-domain" determine whether the node can have
> > children?
> >     Is that really what you intend?
> > 
> >     Should be explained in the commit log and could have been its
> > own
> >     patch, too.
hi, Bjorn,
Yes, this is my intention,"Linux,pci-domain" has two purposes
1)Distinguish the old and new dts formats, then parse them
2)Determine the current pcie slot num in new dts format, because the
offset of some regs needs to be based on slot num

I will split this patch into three patches, and then explain them in
commit log, thanks for your comment.
> 
> I agree with Bjorn, this patch should be split (and commit logs
> rewritten). I will drop it from my tree, waiting for a v12.
> 
> Lorenzo

hi, Lorenzo
Thanks for your confirmation, I will send the V12 version as soon as
possible.

Chuanjia
> 
> > > Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
> > > Acked-by: Ryder Lee <ryder.lee@mediatek.com>
> > > ---
> > >  drivers/pci/controller/pcie-mediatek.c | 52 +++++++++++++++++++-
> > > ------
> > >  1 file changed, 39 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/pcie-mediatek.c
> > > b/drivers/pci/controller/pcie-mediatek.c
> > > index 25bee693834f..928e0983a900 100644
> > > --- a/drivers/pci/controller/pcie-mediatek.c
> > > +++ b/drivers/pci/controller/pcie-mediatek.c
> > > @@ -14,6 +14,7 @@
> > >  #include <linux/irqchip/chained_irq.h>
> > >  #include <linux/irqdomain.h>
> > >  #include <linux/kernel.h>
> > > +#include <linux/mfd/syscon.h>
> > >  #include <linux/msi.h>
> > >  #include <linux/module.h>
> > >  #include <linux/of_address.h>
> > > @@ -23,6 +24,7 @@
> > >  #include <linux/phy/phy.h>
> > >  #include <linux/platform_device.h>
> > >  #include <linux/pm_runtime.h>
> > > +#include <linux/regmap.h>
> > >  #include <linux/reset.h>
> > >  
> > >  #include "../pci.h"
> > > @@ -207,6 +209,7 @@ struct mtk_pcie_port {
> > >   * struct mtk_pcie - PCIe host information
> > >   * @dev: pointer to PCIe device
> > >   * @base: IO mapped register base
> > > + * @cfg: IO mapped register map for PCIe config
> > >   * @free_ck: free-run reference clock
> > >   * @mem: non-prefetchable memory resource
> > >   * @ports: pointer to PCIe port information
> > > @@ -215,6 +218,7 @@ struct mtk_pcie_port {
> > >  struct mtk_pcie {
> > >  	struct device *dev;
> > >  	void __iomem *base;
> > > +	struct regmap *cfg;
> > >  	struct clk *free_ck;
> > >  
> > >  	struct list_head ports;
> > > @@ -650,7 +654,11 @@ static int mtk_pcie_setup_irq(struct
> > > mtk_pcie_port *port,
> > >  		return err;
> > >  	}
> > >  
> > > -	port->irq = platform_get_irq(pdev, port->slot);
> > > +	if (of_find_property(dev->of_node, "interrupt-names", NULL))
> > > +		port->irq = platform_get_irq_byname(pdev, "pcie_irq");
> > > +	else
> > > +		port->irq = platform_get_irq(pdev, port->slot);
> > > +
> > >  	if (port->irq < 0)
> > >  		return port->irq;
> > >  
> > > @@ -682,6 +690,10 @@ static int mtk_pcie_startup_port_v2(struct
> > > mtk_pcie_port *port)
> > >  		val |= PCIE_CSR_LTSSM_EN(port->slot) |
> > >  		       PCIE_CSR_ASPM_L1_EN(port->slot);
> > >  		writel(val, pcie->base + PCIE_SYS_CFG_V2);
> > > +	} else if (pcie->cfg) {
> > > +		val = PCIE_CSR_LTSSM_EN(port->slot) |
> > > +		      PCIE_CSR_ASPM_L1_EN(port->slot);
> > > +		regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val,
> > > val);
> > >  	}
> > >  
> > >  	/* Assert all reset signals */
> > > @@ -985,6 +997,7 @@ static int mtk_pcie_subsys_powerup(struct
> > > mtk_pcie *pcie)
> > >  	struct device *dev = pcie->dev;
> > >  	struct platform_device *pdev = to_platform_device(dev);
> > >  	struct resource *regs;
> > > +	struct device_node *cfg_node;
> > >  	int err;
> > >  
> > >  	/* get shared registers, which are optional */
> > > @@ -995,6 +1008,14 @@ static int mtk_pcie_subsys_powerup(struct
> > > mtk_pcie *pcie)
> > >  			return PTR_ERR(pcie->base);
> > >  	}
> > >  
> > > +	cfg_node = of_find_compatible_node(NULL, NULL,
> > > +					   "mediatek,generic-pciecfg");
> > > +	if (cfg_node) {
> > > +		pcie->cfg = syscon_node_to_regmap(cfg_node);
> > > +		if (IS_ERR(pcie->cfg))
> > > +			return PTR_ERR(pcie->cfg);
> > > +	}
> > > +
> > >  	pcie->free_ck = devm_clk_get(dev, "free_ck");
> > >  	if (IS_ERR(pcie->free_ck)) {
> > >  		if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
> > > @@ -1027,22 +1048,27 @@ static int mtk_pcie_setup(struct mtk_pcie
> > > *pcie)
> > >  	struct device *dev = pcie->dev;
> > >  	struct device_node *node = dev->of_node, *child;
> > >  	struct mtk_pcie_port *port, *tmp;
> > > -	int err;
> > > +	int err, slot;
> > > +
> > > +	slot = of_get_pci_domain_nr(dev->of_node);
> > > +	if (slot < 0) {
> > > +		for_each_available_child_of_node(node, child) {
> > > +			err = of_pci_get_devfn(child);
> > > +			if (err < 0) {
> > > +				dev_err(dev, "failed to get devfn:
> > > %d\n", err);
> > > +				goto error_put_node;
> > > +			}
> > >  
> > > -	for_each_available_child_of_node(node, child) {
> > > -		int slot;
> > > +			slot = PCI_SLOT(err);
> > >  
> > > -		err = of_pci_get_devfn(child);
> > > -		if (err < 0) {
> > > -			dev_err(dev, "failed to parse devfn: %d\n",
> > > err);
> > > -			goto error_put_node;
> > > +			err = mtk_pcie_parse_port(pcie, child, slot);
> > > +			if (err)
> > > +				goto error_put_node;
> > >  		}
> > > -
> > > -		slot = PCI_SLOT(err);
> > > -
> > > -		err = mtk_pcie_parse_port(pcie, child, slot);
> > > +	} else {
> > > +		err = mtk_pcie_parse_port(pcie, node, slot);
> > >  		if (err)
> > > -			goto error_put_node;
> > > +			return err;
> > >  	}
> > >  
> > >  	err = mtk_pcie_subsys_powerup(pcie);
> > > -- 
> > > 2.18.0
> > > 

  reply	other threads:[~2021-08-17 11:19 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-19  7:34 [PATCH v11 0/4] PCI: mediatek: Spilt PCIe node to comply with hardware design Chuanjia Liu
2021-07-19  7:34 ` [PATCH v11 1/4] dt-bindings: PCI: mediatek: Update the Device tree bindings Chuanjia Liu
2021-07-19 22:47   ` Rob Herring
2021-07-20  2:07     ` Chuanjia Liu
2021-07-20 16:26       ` Rob Herring
2021-07-23  7:17         ` Chuanjia Liu
2021-07-19  7:34 ` [PATCH v11 2/4] PCI: mediatek: Add new method to get shared pcie-cfg base address and parse node Chuanjia Liu
2021-07-20  2:59   ` Chuanjia Liu
2021-08-03 22:18     ` Rob Herring
2021-08-06  7:37       ` Chuanjia Liu (柳传嘉)
2021-08-02  7:07   ` Chuanjia Liu
2021-08-10 19:42   ` Bjorn Helgaas
2021-08-13 15:22     ` Lorenzo Pieralisi
2021-08-17 11:18       ` Chuanjia Liu (柳传嘉) [this message]
2021-07-19  7:34 ` [PATCH v11 3/4] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 Chuanjia Liu
2021-07-19  7:34 ` [PATCH v11 4/4] ARM: dts: mediatek: Update MT7629 PCIe node for new format Chuanjia Liu
2021-08-06  9:39 ` [PATCH v11 0/4] PCI: mediatek: Spilt PCIe node to comply with hardware design Lorenzo Pieralisi
2021-08-08  4:50   ` Chuanjia Liu (柳传嘉)

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