LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: <Conor.Dooley@microchip.com>
To: <krzysztof.kozlowski@canonical.com>, <robh+dt@kernel.org>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <atish.patra@wdc.com>,
	<sagar.kadam@sifive.com>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic
Date: Tue, 31 Aug 2021 11:27:24 +0000	[thread overview]
Message-ID: <5b05d1e0-24be-f013-bb4e-f69b061b62e4@microchip.com> (raw)
In-Reply-To: <20210825130639.203657-1-krzysztof.kozlowski@canonical.com>

On 25/08/2021 14:06, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
> also Core Local Interruptor and Platform-Level Interrupt Controller are
> coming from SiFive.  Add proper compatibles to silence dtbs_check
> warnings:
>
>    clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
>    interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
> ---
>
> Changes since v1:
> 1. None
> ---
>   arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index d9f7ee747d0d..6f843afacfad 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -161,7 +161,7 @@ cache-controller@2010000 {
>                  };
>
>                  clint@2000000 {
> -                       compatible = "sifive,clint0";
> +                       compatible = "sifive,fu540-c000-clint", "sifive,clint0";
>                          reg = <0x0 0x2000000 0x0 0xC000>;
>                          interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>                                                  &cpu1_intc 3 &cpu1_intc 7
> @@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
>
>                  plic: interrupt-controller@c000000 {
>                          #interrupt-cells = <1>;
> -                       compatible = "sifive,plic-1.0.0";
> +                       compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>                          reg = <0x0 0xc000000 0x0 0x4000000>;
>                          riscv,ndev = <186>;
>                          interrupt-controller;
> --
> 2.30.2
>
Looks good, we've switched to using this one ourselves also.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



  reply	other threads:[~2021-08-31 11:27 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 13:04 [PATCH v2 1/5] riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 2/5] riscv: dts: sifive: fix Unleashed board compatible Krzysztof Kozlowski
2021-08-25 13:04 ` [PATCH v2 3/5] riscv: dts: sifive: drop duplicated nodes and properties in sifive Krzysztof Kozlowski
2021-08-25 13:06 ` Krzysztof Kozlowski
2021-08-25 13:06 ` [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic Krzysztof Kozlowski
2021-08-31 11:27   ` Conor.Dooley [this message]
2021-08-25 13:07 ` [PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Krzysztof Kozlowski

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5b05d1e0-24be-f013-bb4e-f69b061b62e4@microchip.com \
    --to=conor.dooley@microchip.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=atish.patra@wdc.com \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski@canonical.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=sagar.kadam@sifive.com \
    --subject='Re: [PATCH v2 4/5] riscv: dts: microchip: add missing compatibles for clint and plic' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).