LKML Archive on
help / color / mirror / Atom feed
From: Michal Simek <>
To: Linus Walleij <>,
	Michal Simek <>
Cc: "" <>,
	Michal Simek <>,
	Steffen Trumtrar <>,
	Peter Crosthwaite <>,
	"open list:GPIO SUBSYSTEM" <>,
	Rob Herring <>,
	Linux ARM <>
Subject: Re: [PATCH] gpio: zynq: Setup chip->base based on alias ID
Date: Wed, 2 May 2018 15:41:12 +0200	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 2.5.2018 15:01, Linus Walleij wrote:
> On Wed, May 2, 2018 at 12:15 PM, Michal Simek <> wrote:
>> On 2.5.2018 12:10, Linus Walleij wrote:
>>> On Thu, Apr 26, 2018 at 3:35 PM, Michal Simek <> wrote:
>>>> Yes, it is about legacy application which I have seen recently and there
>>>> is no source code for application calls it because board vendor doesn't
>>>> provide it.
>>>> You are right that -1 was used from the beginning in mainline but
>>>> unfortunately this driver was in vendor tree for a while and it uses 0
>>>> there.
>>>> In upstreaming this was changed to -1 but customers have a lot of code
>>>> which developed against vendor tree and they want to use
>>>> latest&greatest. And without this they are not able to run that
>>>> applications.
>>>> I found that this logic is already in 5 drivers in mainline that's why I
>>>> send this patch to be +1.
>>> I see.
>>> Sadly comaptibility with out-of-tree driver code is none of our
>>> (community) business.
>>> We do pay a lot of effort not to break the ABI to userspace, but
>>> it needs to be an ABI coming from the mainline kernel, not from
>>> a vendor tree.
>>> So to the mainline kernel this is no regression.
>> I understand your statement. On the other hand it is feature which was
>> permitted in past for some drivers and this is +1.
> But was it permitted because of breaking out of tree code?

You know how soc vendors are working. We need to develop code out of
mainline for certain time because we can't share details before.

When we get permission to upstream code a lot of application code is
done already with certain expectation.

Soren has sent this driver with using -1 for autodetection even at that
time Xilinx gpio driver had 0 there.

This patch is not breaking any current functionality and there is no any
gpio alias in zynq/zynqmp too. And from my point of view the usage of
gpio alias is similar to others aliases present in DTS file.

If you don't want this patch I understand that and it will become just
another soc vendor patch out of mainline.


  reply	other threads:[~2018-05-02 13:41 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-11 13:55 Michal Simek
2018-04-26 13:08 ` Linus Walleij
2018-04-26 13:35   ` Michal Simek
2018-05-02 10:10     ` Linus Walleij
2018-05-02 10:15       ` Michal Simek
2018-05-02 13:01         ` Linus Walleij
2018-05-02 13:41           ` Michal Simek [this message]
2018-05-02 13:56             ` Linus Walleij
2018-05-02 14:19               ` Michal Simek
2018-05-15 13:26                 ` Michal Simek
2018-05-23  9:44                   ` Linus Walleij
2018-05-23 10:26                     ` Michal Simek
2018-05-23  9:42                 ` Linus Walleij
2018-05-23 10:17                   ` Michal Simek

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \ \ \ \ \ \ \ \ \ \ \
    --subject='Re: [PATCH] gpio: zynq: Setup chip->base based on alias ID' \

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).