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From: Matt Redfearn <matt.redfearn@mips.com>
To: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Florian Fainelli <f.fainelli@gmail.com>,
<linux-mips@linux-mips.org>, Namhyung Kim <namhyung@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
<linux-kernel@vger.kernel.org>, Ingo Molnar <mingo@redhat.com>,
Jiri Olsa <jolsa@redhat.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>
Subject: Re: [PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads
Date: Thu, 17 May 2018 11:35:17 +0100 [thread overview]
Message-ID: <63a1ca19-6ded-149a-5a61-7464609c691b@mips.com> (raw)
In-Reply-To: <20180516175916.GA12837@jamesdev>
Hi James,
On 16/05/18 18:59, James Hogan wrote:
> On Fri, Apr 20, 2018 at 11:23:06AM +0100, Matt Redfearn wrote:
>> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
>> index 7e2b7d38a774..fe50986e83c6 100644
>> --- a/arch/mips/kernel/perf_event_mipsxx.c
>> +++ b/arch/mips/kernel/perf_event_mipsxx.c
>> @@ -323,7 +323,11 @@ static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
>>
>> static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
>> {
>> + struct perf_event *event = container_of(evt, struct perf_event, hw);
>> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>> +#ifdef CONFIG_MIPS_MT_SMP
>> + unsigned int range = evt->event_base >> 24;
>> +#endif /* CONFIG_MIPS_MT_SMP */
>>
>> WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
>>
>> @@ -331,11 +335,37 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
>> (evt->config_base & M_PERFCTL_CONFIG_MASK) |
>> /* Make sure interrupt enabled. */
>> MIPS_PERFCTRL_IE;
>> - if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
>> +
>> +#ifdef CONFIG_CPU_BMIPS5000
>> + {
>> /* enable the counter for the calling thread */
>> cpuc->saved_ctrl[idx] |=
>> (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
>> + }
>> +#else
>> +#ifdef CONFIG_MIPS_MT_SMP
>> + if (range > V) {
>> + /* The counter is processor wide. Set it up to count all TCs. */
>> + pr_debug("Enabling perf counter for all TCs\n");
>> + cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
>> + } else
>> +#endif /* CONFIG_MIPS_MT_SMP */
>> + {
>> + unsigned int cpu, ctrl;
>>
>> + /*
>> + * Set up the counter for a particular CPU when event->cpu is
>> + * a valid CPU number. Otherwise set up the counter for the CPU
>> + * scheduling this thread.
>> + */
>> + cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
>> +
>> + ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
>> + ctrl |= M_TC_EN_VPE;
>> + cpuc->saved_ctrl[idx] |= ctrl;
>> + pr_debug("Enabling perf counter for CPU%d\n", cpu);
>> + }
>> +#endif /* CONFIG_CPU_BMIPS5000 */
>
> I'm not a huge fan of the ifdefery tbh, I don't think it makes it very
> easy to read having a combination of ifs and #ifdefs. I reckon
> IF_ENABLED would be better, perhaps with having the BMIPS5000 case
> return to avoid too much nesting.
OK, I'll try and tidy it up.
Thanks,
Matt
>
> Otherwise the patch looks okay to me.
>
> Thanks
> James
>
next prev parent reply other threads:[~2018-05-17 10:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-20 10:23 [PATCH v3 0/7] MIPS: perf: MT fixes and improvements Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 1/7] MIPS: Probe for MIPS MT perf counters per TC Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 2/7] MIPS: perf: More robustly probe for the presence of per-tc counters Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 3/7] MIPS: perf: Use correct VPE ID when setting up VPE tracing Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 4/7] MIPS: perf: Fix perf with MT counting other threads Matt Redfearn
2018-05-16 17:59 ` James Hogan
2018-05-17 10:35 ` Matt Redfearn [this message]
2018-04-20 10:23 ` [PATCH v3 5/7] MIPS: perf: Allocate per-core counters on demand Matt Redfearn
2018-05-16 18:05 ` James Hogan
2018-05-17 10:40 ` Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 6/7] MIPS: perf: Fold vpe_id() macro into it's one last usage Matt Redfearn
2018-04-20 10:23 ` [PATCH v3 7/7] MIPS: perf: Fix BMIPS5000 system mode counting Matt Redfearn
2018-05-15 14:44 ` [PATCH v4] " Matt Redfearn
2018-04-20 22:51 ` [PATCH v3 0/7] MIPS: perf: MT fixes and improvements Florian Fainelli
2018-04-23 13:40 ` Matt Redfearn
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