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From: Frank Wunderlich <linux@fw-web.de>
To: Hsin-Yi Wang <hsinyi@chromium.org>
Cc: "moderated list:ARM/Mediatek SoC support" 
	<linux-mediatek@lists.infradead.org>, CK Hu <ck.hu@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	lkml <linux-kernel@vger.kernel.org>,
	stable@vger.kernel.org,
	Frank Wunderlich <frank-w@public-files.de>
Subject: Re: [PATCH] soc: mmsys: mediatek: add mask to mmsys routes
Date: Thu, 29 Jul 2021 07:53:58 +0200	[thread overview]
Message-ID: <6BFE13A3-6A42-455E-BDF7-CD285CC6C66D@fw-web.de> (raw)
In-Reply-To: <CAJMQK-gQeMidjBZ1E=ReMmffC5G8oiFawB4Ey1PNb2ZWXw_1Bg@mail.gmail.com>

Am 29. Juli 2021 07:47:03 MESZ schrieb Hsin-Yi Wang <hsinyi@chromium.org>:
>On Thu, Jul 29, 2021 at 1:40 PM Frank Wunderlich <linux@fw-web.de>
>wrote:
>>
>
>>
> struct mtk_mmsys_routes {
>         u32 from_comp;
>         u32 to_comp;
>         u32 addr;
> +       u32 mask;
>         u32 val;
>  };
>mask is not the last element, and mmsys_mt8183_routing_table = {
>  {
>    DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
>    MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
>  }
>...
>so the mask and val will be wrong. CK, do you know what mask we should
>set for mt8183? Or can we just set a dummy 0 mask.

Ahhh...mt8183 has own mmsys-table and
i had only changed the default one,so
value is now missing because value is now the mask. I have used same order as
CK to avoid confusion and make it easier
to review.
Afaik you could use same value as value to reset same bits...did this in default routing table too.

regards Frank

  reply	other threads:[~2021-07-29  5:54 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 17:40 Frank Wunderlich
2021-07-28 23:37 ` Chun-Kuang Hu
2021-07-29  3:15 ` Hsin-Yi Wang
2021-07-29  3:42   ` CK Hu
2021-07-29  5:40   ` Frank Wunderlich
2021-07-29  5:47     ` Hsin-Yi Wang
2021-07-29  5:53       ` Frank Wunderlich [this message]
2021-07-29  5:58         ` Hsin-Yi Wang
2021-07-29  6:45           ` Frank Wunderlich
2021-07-29  6:47             ` Hsin-Yi Wang

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