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From: Wei Huang <wei.huang2@amd.com>
To: Yu Zhang <yu.c.zhang@linux.intel.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com,
	wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org,
	tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
	x86@kernel.org, hpa@zytor.com
Subject: Re: [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level
Date: Sun, 8 Aug 2021 23:33:44 -0500	[thread overview]
Message-ID: <73bbaac0-701c-42dd-36da-aae1fed7f1a0@amd.com> (raw)
In-Reply-To: <20210809042703.25gfuuvujicc3vj7@linux.intel.com>



On 8/8/21 11:27 PM, Yu Zhang wrote:
> On Sun, Aug 08, 2021 at 11:11:40PM -0500, Wei Huang wrote:
>>
>>
>> On 8/8/21 10:58 PM, Yu Zhang wrote:
>>> On Sun, Aug 08, 2021 at 02:26:56PM -0500, Wei Huang wrote:
>>>> AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set.
>>>
>>> Sorry, but why? NPT is not indexed by HVA.
>>
>> NPT is not indexed by HVA - it is always indexed by GPA. What I meant is NPT
>> page table level has to be the same as the host OS page table: if 5-level
>> page table is enabled in host OS (CR4.LA57=1), guest NPT has to 5-level too.
> 
> I know what you meant. But may I ask why?

I don't have a good answer for it. From what I know, VMCB doesn't have a 
field to indicate guest page table level. As a result, hardware relies 
on host CR4 to infer NPT level.

> 
> B.R.
> Yu
> 
>>

  reply	other threads:[~2021-08-09  4:34 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-08 19:26 [PATCH v2 0/3] SVM 5-level page table support Wei Huang
2021-08-08 19:26 ` [PATCH v2 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level Wei Huang
2021-08-09  3:58   ` Yu Zhang
2021-08-09  4:11     ` Wei Huang
2021-08-09  4:27       ` Yu Zhang
2021-08-09  4:33         ` Wei Huang [this message]
2021-08-09  6:42           ` Yu Zhang
2021-08-09 15:30             ` Sean Christopherson
2021-08-09 21:49               ` Jim Mattson
2021-08-10  9:23                 ` Paolo Bonzini
2021-08-10  7:40               ` Yu Zhang
2021-08-10  9:25                 ` Paolo Bonzini
2021-08-10 11:00                   ` Yu Zhang
2021-08-10 12:47                     ` Paolo Bonzini
2021-08-10 14:37                       ` Yu Zhang
2021-08-08 19:26 ` [PATCH v2 2/3] KVM: x86: Handle the case of 5-level shadow page table Wei Huang
2021-08-09 15:17   ` Sean Christopherson
2021-08-09 17:03     ` Wei Huang
2021-08-08 19:26 ` [PATCH v2 3/3] KVM: SVM: Add 5-level page table support for SVM Wei Huang

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