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* [PATCH 0/3] perfmon x86 infrastructure definitions (take 2)
@ 2008-03-07 21:05 stephane eranian
  2008-03-10  7:52 ` Ingo Molnar
  0 siblings, 1 reply; 3+ messages in thread
From: stephane eranian @ 2008-03-07 21:05 UTC (permalink / raw)
  To: linux-kernel; +Cc: Andrew Morton, ak, Ingo Molnar, tglx

Hello,

Take 2: correct titles and no attachment.

Here is a small set of patches for x86. They are used by perfmon
but they can be applied independently.

patch 1: adds cpu_has_arch_perfmon to cpufeature macros to test for
architectural perfmon  on Intel processors
patch 2: adds AMD Northbridge config MSR definition
patch 3: adds AMD Northbridge PCI Id

Please apply.
Thanks.

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH 0/3] perfmon x86 infrastructure definitions (take 2)
  2008-03-07 21:05 [PATCH 0/3] perfmon x86 infrastructure definitions (take 2) stephane eranian
@ 2008-03-10  7:52 ` Ingo Molnar
  2008-03-11 16:37   ` stephane eranian
  0 siblings, 1 reply; 3+ messages in thread
From: Ingo Molnar @ 2008-03-10  7:52 UTC (permalink / raw)
  To: stephane eranian; +Cc: linux-kernel, Andrew Morton, ak, tglx


* stephane eranian <eranian@googlemail.com> wrote:

> Hello,
> 
> Take 2: correct titles and no attachment.

note, all the patches were whitespace damaged (all tabs were spaces). I 
fixed this up by hand but please check Documentation/email-clients.txt.

> Here is a small set of patches for x86. They are used by perfmon but 
> they can be applied independently.
> 
> patch 1: adds cpu_has_arch_perfmon to cpufeature macros to test for
> architectural perfmon  on Intel processors
> patch 2: adds AMD Northbridge config MSR definition
> patch 3: adds AMD Northbridge PCI Id

i've added all three to x86.git for convenience, but the PCI ID will 
need to go via Greg KH's PCI tree i suspect.

	Ingo

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH 0/3] perfmon x86 infrastructure definitions (take 2)
  2008-03-10  7:52 ` Ingo Molnar
@ 2008-03-11 16:37   ` stephane eranian
  0 siblings, 0 replies; 3+ messages in thread
From: stephane eranian @ 2008-03-11 16:37 UTC (permalink / raw)
  To: Ingo Molnar; +Cc: linux-kernel, Andrew Morton, ak, tglx

Ingo,

Thanks. Will send the PCI id patch to Greg KH.


On Mon, Mar 10, 2008 at 12:52 AM, Ingo Molnar <mingo@elte.hu> wrote:
>
>  * stephane eranian <eranian@googlemail.com> wrote:
>
>  > Hello,
>  >
>  > Take 2: correct titles and no attachment.
>
>  note, all the patches were whitespace damaged (all tabs were spaces). I
>  fixed this up by hand but please check Documentation/email-clients.txt.
>
>
>  > Here is a small set of patches for x86. They are used by perfmon but
>  > they can be applied independently.
>  >
>  > patch 1: adds cpu_has_arch_perfmon to cpufeature macros to test for
>  > architectural perfmon  on Intel processors
>  > patch 2: adds AMD Northbridge config MSR definition
>  > patch 3: adds AMD Northbridge PCI Id
>
>  i've added all three to x86.git for convenience, but the PCI ID will
>  need to go via Greg KH's PCI tree i suspect.
>
>         Ingo
>

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2008-03-11 16:37 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2008-03-07 21:05 [PATCH 0/3] perfmon x86 infrastructure definitions (take 2) stephane eranian
2008-03-10  7:52 ` Ingo Molnar
2008-03-11 16:37   ` stephane eranian

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