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From: Marc Zyngier <maz@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	LKML <linux-kernel@vger.kernel.org>,
	Alex Williamson <alex.williamson@redhat.com>,
	"Raj, Ashok" <ashok.raj@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Kevin Tian <kevin.tian@intel.com>, Ingo Molnar <mingo@kernel.org>,
	"x86@kernel.org" <x86@kernel.org>
Subject: Re: [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible
Date: Fri, 23 Jul 2021 09:14:10 +0100	[thread overview]
Message-ID: <8735s530rx.wl-maz@kernel.org> (raw)
In-Reply-To: <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>

On Thu, 22 Jul 2021 22:54:48 +0100,
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> 
> [1  <text/plain; UTF-8 (7bit)>]
> On Friday, July 23, 2021, Bjorn Helgaas <helgaas@kernel.org> wrote:
> 
> > On Wed, Jul 21, 2021 at 09:11:30PM +0200, Thomas Gleixner wrote:
> > > Nothing enforces the posted writes to be visible when the function
> > > returns. Flush them even if the flush might be redundant when the entry
> > is
> > > masked already as the unmask will flush as well. This is either setup or
> > a
> > > rare affinity change event so the extra flush is not the end of the
> > world.
> > >
> > > While this is more a theoretical issue especially the X86 MSI affinity
> > > stter mechanism relies on the assumption that the update has reached the
> >
> > stter?
> 
> 
> Setter I suppose

My bet is on 'steer', given that this is about affinity management.

	M.

-- 
Without deviation from the norm, progress is not possible.

  parent reply	other threads:[~2021-07-23  8:14 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 19:11 [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner
2021-07-21 19:11 ` [patch 1/8] PCI/MSI: Enable and mask MSIX early Thomas Gleixner
2021-07-21 21:38   ` Raj, Ashok
2021-07-21 22:51     ` Thomas Gleixner
2021-07-22 21:43   ` Bjorn Helgaas
2021-07-27 20:33     ` Thomas Gleixner
2021-07-21 19:11 ` [patch 2/8] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner
2021-07-21 22:23   ` Raj, Ashok
2021-07-21 22:57     ` Thomas Gleixner
2021-07-22 13:46       ` Marc Zyngier
2021-07-28 10:04         ` Thomas Gleixner
2021-07-22 21:45   ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner
2021-07-21 22:32   ` Raj, Ashok
2021-07-21 22:59     ` Thomas Gleixner
2021-07-22 21:46   ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner
2021-07-22 21:48   ` Bjorn Helgaas
     [not found]     ` <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>
2021-07-23  8:14       ` Marc Zyngier [this message]
2021-07-21 19:11 ` [patch 5/8] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner
2021-07-21 19:11 ` [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner
2021-07-22 15:12   ` Marc Zyngier
2021-07-28 10:40     ` Thomas Gleixner
2021-07-21 19:11 ` [patch 7/8] x86/ioapic: Force affinity setup before startup Thomas Gleixner
2021-07-21 19:11 ` [patch 8/8] x86/msi: " Thomas Gleixner
2021-07-21 21:10 ` [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Raj, Ashok
2021-07-21 22:39   ` Thomas Gleixner
2021-07-22 15:17 ` Marc Zyngier
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:38   ` Thomas Gleixner

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