From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D304C4338F for ; Mon, 23 Aug 2021 12:17:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0DB7661184 for ; Mon, 23 Aug 2021 12:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236896AbhHWMRu (ORCPT ); Mon, 23 Aug 2021 08:17:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:45564 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236173AbhHWMRs (ORCPT ); Mon, 23 Aug 2021 08:17:48 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F39546138F; Mon, 23 Aug 2021 12:17:05 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mI8sy-006ene-4D; Mon, 23 Aug 2021 13:17:04 +0100 Date: Mon, 23 Aug 2021 13:17:03 +0100 Message-ID: <874kbgqrsw.wl-maz@kernel.org> From: Marc Zyngier To: Valentin Schneider Cc: Guenter Roeck , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] irqchip/gic: Convert to handle_strict_flow_irq() In-Reply-To: <875yvw78e5.mognet@arm.com> References: <20210814194737.GA3951530@roeck-us.net> <87sfzb7jeo.mognet@arm.com> <87eeav19mc.wl-maz@kernel.org> <87k0kk7w0c.mognet@arm.com> <87czqasn9u.wl-maz@kernel.org> <878s0t6s7p.mognet@arm.com> <87czq4qzd7.wl-maz@kernel.org> <875yvw78e5.mognet@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: valentin.schneider@arm.com, linux@roeck-us.net, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 23 Aug 2021 11:38:58 +0100, Valentin Schneider wrote: > > On 23/08/21 10:33, Marc Zyngier wrote: > > On Sun, 22 Aug 2021 23:16:10 +0100, > > Valentin Schneider wrote: > >> > >> On 18/08/21 17:58, Marc Zyngier wrote: > >> > There is the bizarre case of drivers/gpio/gpio-thunderx.c that changes > >> > the irqchip flow to use either handle_fasteoi_ack_irq or > >> > handle_fasteoi_mask_irq, which won't play very nicely with this. > >> > Someone said Cavium? > >> > > >> > >> Humph... > >> > >> I'm not familiar at all with the gpiolib irqchips, but I was under the > >> impression those would involve chained IRQs (it does appear to be the case > >> for the pl061 GPIOs on a Juno). For those, the innermost desc would be handled > >> via chained_irq_{enter, exit}() [!!!], and the outermost one via whatever > >> flow was installed by the relevant driver. > > > > Not all of them are built like this. There is actually a bunch of > > these build as full hierarchies (QC, nvidia and some others). > > > > I see, thanks! > > >> I can't easily grok what goes on between that gpio-thunderx.c driver and > >> gpiolib, but since that GPIO chip has > >> > >> .irq_eoi = irq_chip_eoi_parent, > >> > >> and > >> > >> girq->parent_domain = > >> irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; > >> > >> (GPIOs hooked to MSI-X? Do I want to know?) > > > > It's good, isn't it? TX1 has all its HW appearing as PCI, even if it > > clearly isn't PCI underneath. > > > >> > >> I'm guessing it is *not* chained, which means the irq_set_handler_locked() > >> affects the entire stack :/ > > > > It does. We can probably fix that, but I won't be able to test (my TX1 > > was taken away a few months ago...). I'll accept body donations, for > > scientific purposes. > > > > Looks like there are still some over on s/packet/equinix/, so I should be > able to poke at one. That's where mine used to live, but the WoA people decided that I really didn't need one, and I'm now only allowed to borrow one of the old eMAGs. If you can pull strings, let me know! :D M. -- Without deviation from the norm, progress is not possible.