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From: Vignesh R <vigneshr@ti.com>
To: Arkadiusz Kwiatkowski <arkadiusz.kwiatkowski@aptiv.com>,
	<broonie@kernel.org>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] spi: spi-ti-qspi: Fix parameters order in regmap_update_bits calls
Date: Tue, 3 Apr 2018 11:33:44 +0530	[thread overview]
Message-ID: <87e92c69-60bb-37b0-87d3-c4c688e94d09@ti.com> (raw)
In-Reply-To: <1522402884-26790-1-git-send-email-arkadiusz.kwiatkowski@aptiv.com>



On Friday 30 March 2018 03:11 PM, Arkadiusz Kwiatkowski wrote:
> This commit fixes the order of parameters passed to regmap_update_bits
> function inside spi-ti-qspi driver. Accidentally the code worked
> correctly when cs=0, but it is not the case for other values.
> 

Add:
Fixes: 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support")
before Signed-off-by

> Signed-off-by: Arkadiusz Kwiatkowski <arkadiusz.kwiatkowski@aptiv.com>
> ---

Unfortunately, your mail client is still mangling the patch and "git am"
 still fails to apply this from my inbox. Could you try using "git
send-email" to send patches? See
https://www.kernel.org/doc/Documentation/process/email-clients.rst for
more info

>  drivers/spi/spi-ti-qspi.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index c24d9b4..d0ea62d 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -490,8 +490,8 @@ static void ti_qspi_enable_memory_map(struct spi_device *spi)
>         ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
>         if (qspi->ctrl_base) {
>                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
> -                                  MEM_CS_EN(spi->chip_select),
> -                                  MEM_CS_MASK);
> +                                  MEM_CS_MASK,
> +                                  MEM_CS_EN(spi->chip_select));
>         }
>         qspi->mmap_enabled = true;
>  }
> @@ -503,7 +503,7 @@ static void ti_qspi_disable_memory_map(struct spi_device *spi)
>         ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
>         if (qspi->ctrl_base)
>                 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
> -                                  0, MEM_CS_MASK);
> +                                  MEM_CS_MASK, 0);
>         qspi->mmap_enabled = false;
>  }
> 
> --
> 2.7.4
> 
> **************************************************************************************** Note: If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by replying to the message and deleting it from your computer. Thank you. ****************************************************************************************
> 

-- 
Regards
Vignesh

  parent reply	other threads:[~2018-04-03  6:03 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 12:33 [PATCH] Fixes in TI QSPI driver to allow more than one flash chip Kwiatkowski, Arkadiusz
2018-03-27  4:00 ` Vignesh R
2018-03-30  9:41   ` [PATCH v2 1/2] spi: spi-ti-qspi: Fix parameters order in regmap_update_bits calls Arkadiusz Kwiatkowski
2018-03-30  9:41     ` [PATCH v2 2/2] spi: spi-ti-qspi: Add checking which flash chip has been mmap-ed Arkadiusz Kwiatkowski
2018-04-03  6:03     ` Vignesh R [this message]
2018-04-03  9:09     ` [PATCH v2 1/2] spi: spi-ti-qspi: Fix parameters order in regmap_update_bits calls Mark Brown
2018-04-16 16:58     ` Mark Brown

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