From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4062C4320A for ; Wed, 11 Aug 2021 18:31:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8711160F46 for ; Wed, 11 Aug 2021 18:31:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230405AbhHKScG (ORCPT ); Wed, 11 Aug 2021 14:32:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:54942 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230343AbhHKScC (ORCPT ); Wed, 11 Aug 2021 14:32:02 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8C89761077; Wed, 11 Aug 2021 18:31:38 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mDt0q-004Oaz-DM; Wed, 11 Aug 2021 19:31:36 +0100 Date: Wed, 11 Aug 2021 19:31:36 +0100 Message-ID: <87fsvfal4n.wl-maz@kernel.org> From: Marc Zyngier To: Chen-Yu Tsai Cc: Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Elisei Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used In-Reply-To: <20210811171505.1502090-1-wenst@chromium.org> References: <20210811171505.1502090-1-wenst@chromium.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: wenst@chromium.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru.Elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org + Alex, who introduced this. On Wed, 11 Aug 2021 18:15:05 +0100, Chen-Yu Tsai wrote: > > When non-secure priorities are used, compared to the raw priority set, > the value read back from RPR is also right-shifted by one and the > highest bit set. > > Add a macro to do the modifications to the raw priority when doing the > comparison against the RPR value. This corrects the pseudo-NMI behavior > when non-secure priorities in the GIC are used. Tested on 5.10 with > the "IPI as pseudo-NMI" series [1] applied on MT8195. > > [1] https://lore.kernel.org/linux-arm-kernel/1604317487-14543-1-git-send-email-sumit.garg@linaro.org/ > > Fixes: 336780590990 ("irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0") > Signed-off-by: Chen-Yu Tsai > --- > drivers/irqchip/irq-gic-v3.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index e0f4debe64e1..e7a0b55413db 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -100,6 +100,15 @@ EXPORT_SYMBOL(gic_pmr_sync); > DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); > EXPORT_SYMBOL(gic_nonsecure_priorities); > > +#define GICD_INT_RPR_PRI(priority) \ > + ({ \ > + u32 __priority = (priority); \ > + if (static_branch_unlikely(&gic_nonsecure_priorities)) \ > + __priority = 0x80 | (__priority >> 1); \ > + \ > + __priority; \ This doesn't reflect what the pseudocode says of a read of ICC_RPR_EL1 AFAICS. When the priority is activated, it is indeed shifted. But a read of RPR does appear to shift things back (and you loose the lowest bit in the process). Please see 'aarch64/support/ICC_RPR_EL1' in the architecture spec. Can you confirm that SCR_EL3.FIQ is set on your system? Thanks, M. > + }) > + > /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ > static refcount_t *ppi_nmi_refs; > > @@ -687,7 +696,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs > return; > > if (gic_supports_nmi() && > - unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { > + unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { > gic_handle_nmi(irqnr, regs); > return; > } -- Without deviation from the norm, progress is not possible.