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From: Sekhar Nori <nsekhar@ti.com>
To: Bartosz Golaszewski <brgl@bgdev.pl>,
	Kevin Hilman <khilman@kernel.org>,
	Russell King <linux@armlinux.org.uk>,
	Boris Brezillon <boris.brezillon@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	David Woodhouse <dwmw2@infradead.org>,
	Brian Norris <computersforpeace@gmail.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Tony Lindgren <tony@atomide.com>,
	Krzysztof Kozlowski <krzk@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>
Subject: Re: [PATCH 01/12] mtd: nand: davinci: store the core chipselect number in platform data
Date: Tue, 1 May 2018 15:23:31 +0530	[thread overview]
Message-ID: <8b7e4588-5a35-6c18-fe60-148d6ccf778c@ti.com> (raw)
In-Reply-To: <3dccc5af-2df1-8374-e4e8-0a8b9ea1ae99@ti.com>

On Tuesday 01 May 2018 02:55 PM, Sekhar Nori wrote:
> On Monday 30 April 2018 01:54 PM, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>
>> We have the 'ti,davinci-chipselect' property in the device tree, but
>> when using platform data the driver silently uses the id field of
>> struct platform_device as the chipselect. This is confusing and we
>> almost broke the nand support again recently after converting the
>> platform to common clock framework (which changed the device id in the
>> clock lookup - the problem is gone now that we no longer acquire the
>> clock in the nand driver.
>>
>> This patch adds a new filed - core_chipsel - to the platform_data.
> 
> s/filed/field
> 
>> Subsequent patches will convert the platforms to using this new field.
> 
> Can you add a comment for this new field too, like how we have for most
> other fields?
> 
> Curious on what 'core' in core_chipsel means. Something to do with
> chip-select offset we have on DA850?

Looks like you may have just picked the terminology from DaVinci NAND
driver (introduced back in 2009). But in this context, it means the
0-indexed chip-select number that of the asynchronous memory interface
to which the NAND device is connected.

So, may be a comment here will suffice.

Thanks,
Sekhar

  reply	other threads:[~2018-05-01  9:54 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-30  8:24 [PATCH 00/12] mtd: nand: davinci: stop using pdev->id as chipselect Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 01/12] mtd: nand: davinci: store the core chipselect number in platform data Bartosz Golaszewski
2018-05-01  9:25   ` Sekhar Nori
2018-05-01  9:53     ` Sekhar Nori [this message]
2018-05-01 10:29       ` Sekhar Nori
2018-05-01 10:39         ` Sekhar Nori
2018-05-02 10:45         ` Bartosz Golaszewski
2018-05-02 15:00           ` Sekhar Nori
2018-04-30  8:24 ` [PATCH 02/12] ARM: davinci: da830-evm: specify the chipselect in davinci_nand_pdata Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 03/12] ARM: davinci: da850-evm: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 04/12] ARM: davinci: dm355-evm: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 05/12] ARM: davinci: dm355-leopard: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 06/12] ARM: davinci: dm365-evm: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 07/12] ARM: davinci: dm644x-evm: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 08/12] ARM: davinci: mityomapl138: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 09/12] ARM: davinci: dm646x-evm: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 10/12] ARM: davinci: neuros-osd2: " Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 11/12] mtd: nand: davinci: stop using pdev->id as chipselect Bartosz Golaszewski
2018-04-30  8:24 ` [PATCH 12/12] ARM: davinci: aemif: stop using pdev->id as nand chipselect Bartosz Golaszewski
2018-04-30 10:09 ` [PATCH 00/12] mtd: nand: davinci: stop using pdev->id as chipselect Boris Brezillon
2018-04-30 16:45   ` Bartosz Golaszewski
2018-04-30 16:47     ` Boris Brezillon
2018-05-01 10:12       ` Sekhar Nori
2018-05-03  9:41       ` Sekhar Nori
2018-05-01 10:31   ` Sekhar Nori
2018-05-01 15:02     ` Boris Brezillon

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