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From: "Sven Peter" <email@example.com>
To: "Jassi Brar" <firstname.lastname@example.org>
Cc: "Rob Herring" <email@example.com>,
"Mark Kettenis" <firstname.lastname@example.org>,
"Hector Martin" <email@example.com>,
"Alyssa Rosenzweig" <firstname.lastname@example.org>,
"Mohamed Mediouni" <email@example.com>,
"Stan Skowronek" <firstname.lastname@example.org>,
"Devicetree List" <email@example.com>,
"Linux Kernel Mailing List" <firstname.lastname@example.org>
Subject: Re: [PATCH 0/3] Apple Mailbox Controller support
Date: Thu, 09 Sep 2021 12:44:46 +0200 [thread overview]
Message-ID: <email@example.com> (raw)
On Wed, Sep 8, 2021, at 22:48, Jassi Brar wrote:
> On Tue, Sep 7, 2021 at 9:55 AM Sven Peter <firstname.lastname@example.org> wrote:
> > Hi,
> > This series adds support for the mailbox HW found in the Apple M1. These SoCs
> > have various co-processors controlling different peripherals (NVMe, display
> > controller, SMC (required for WiFi), Thunderbolt, and probably more
> > we don't know about yet). All these co-processors communicate with the main CPU
> > using these mailboxes. These mailboxes transmit 64+32 bit messages, are
> > backed by a hardware FIFO and have four interrupts (FIFO empty and FIFO not
> > empty for the transmit and receive FIFO each).
> > The hardware itself allows to send 64+32 bit message using two hardware
> > registers. A write to or read from the second register transmits or receives a
> > message. Usually, the first 64 bit register is used for the message itself and
> > 8 bits of the second register are used as an endpoint. I originally considered
> > to have the endpoint exposed as a mailbox-channel, but finally decided against
> > it: The hardware itself only provides a single channel to the co-processor and
> > the endpoint bits are only an implementation detail of the firmware. There's
> > even one co-processor (SEP) which uses 8 bits of the first register as its
> > endpoint number instead.
> > There was a similar discussion about the BCM2835 / Raspberry Pi mailboxes
> > which came to the same conclusion .
> > These mailboxes also have a hardware FIFO which make implementing them with the
> > current mailbox a bit tricky: There is no "transmission done" interrupt because
> > most transmissions are "done" immediately. There is only a "transmission fifo
> > empty" level interrupt. I have instead implemented this by adding a fast-path to
> > the core mailbox code as a new txready_fifo mode.
> > The other possibilities (which would not require any changes to the core mailbox
> > code) are to either use the polling mode or to enable the "tx fifo empty"
> > interrupt in send_message and then call txready from the irq handler before
> > disabling it again. I'd like to avoid those though since so far I've never seen
> > the TX FIFO run full which allows to almost always avoid the context switch when
> > sending a message. I can easily switch to one of these modes if you prefer to
> > keep the core code untouched though.
> Yes, please keep the api unchanged.
> Let us please not dig our own tunnels when the existing ways serve the purpose.
Ok, I'll use txdone_irq for v2 then and just ignore the HW FIFO.
prev parent reply other threads:[~2021-09-09 10:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-07 14:54 Sven Peter
2021-09-07 14:54 ` [PATCH 1/3] mailbox: Add txdone_fifo Sven Peter
2021-09-07 14:55 ` [PATCH 2/3] dt-bindings: mailbox: Add Apple mailbox bindings Sven Peter
2021-09-07 18:56 ` Alyssa Rosenzweig
2021-09-07 20:26 ` Sven Peter
2021-09-07 20:48 ` Alyssa Rosenzweig
2021-09-08 15:36 ` Sven Peter
2021-09-11 13:16 ` Mark Kettenis
2021-09-07 14:55 ` [PATCH 3/3] mailbox: apple: Add driver for Apple mailboxes Sven Peter
2021-09-07 18:54 ` Alyssa Rosenzweig
2021-09-07 20:23 ` Sven Peter
2021-09-07 21:06 ` Alyssa Rosenzweig
2021-09-08 15:38 ` Sven Peter
2021-09-08 20:48 ` [PATCH 0/3] Apple Mailbox Controller support Jassi Brar
2021-09-09 10:44 ` Sven Peter [this message]
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