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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Jami Kettunen <jami.kettunen@somainline.org>,
	linux-arm-msm@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@somainline.org>,
	Konrad Dybcio <konrad.dybcio@somainline.org>,
	Martin Botka <martin.botka@somainline.org>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
	Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Krishna Manikandan <quic_mkrishn@quicinc.com>,
	Kalyan Thota <quic_kalyant@quicinc.com>,
	dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum
Date: Wed, 9 Feb 2022 04:49:53 +0300	[thread overview]
Message-ID: <8d710de8-f340-f15a-30c0-3358536bb4f5@linaro.org> (raw)
In-Reply-To: <20220113145111.29984-2-jami.kettunen@somainline.org>

On 13/01/2022 17:51, Jami Kettunen wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> 
> The enum dpu_clk_ctrl_type misses DPU_CLK_CTRL_DMA{2,3} even though
> this driver does actually handle both, if present: add the two in
> preparation for adding support for SoCs having them.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> Signed-off-by: Jami Kettunen <jami.kettunen@somainline.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 31af04afda7d..736f52c742fb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -435,6 +435,8 @@ enum dpu_clk_ctrl_type {
>   	DPU_CLK_CTRL_RGB3,
>   	DPU_CLK_CTRL_DMA0,
>   	DPU_CLK_CTRL_DMA1,
> +	DPU_CLK_CTRL_DMA2,
> +	DPU_CLK_CTRL_DMA3,
>   	DPU_CLK_CTRL_CURSOR0,
>   	DPU_CLK_CTRL_CURSOR1,
>   	DPU_CLK_CTRL_INLINE_ROT0_SSPP,


-- 
With best wishes
Dmitry

  reply	other threads:[~2022-02-09  2:45 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20220113145111.29984-1-jami.kettunen@somainline.org>
2022-01-13 14:51 ` Jami Kettunen
2022-02-09  1:49   ` Dmitry Baryshkov [this message]
2022-01-13 14:51 ` [PATCH 2/3] drm/msm/dpu1: Add MSM8998 to hw catalog Jami Kettunen
2022-02-09 21:57   ` Dmitry Baryshkov
2022-01-13 14:51 ` [PATCH 3/3] dt-bindings: display: msm: Add binding for msm8998 dpu Jami Kettunen
2022-02-09  2:23   ` Rob Herring
2021-09-01 18:11 [PATCH 1/3] drm/msm/dpu1: Add DMA2, DMA3 clock control to enum AngeloGioacchino Del Regno
2021-09-02 22:21 ` Dmitry Baryshkov
2021-09-03 18:24 ` Dmitry Baryshkov

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