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From: Deepak Sharma <deesharm@amd.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>,
	Deepak Sharma <deepak.sharma@amd.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
	<x86@kernel.org>, "H. Peter Anvin" <hpa@zytor.com>,
	"open list:SUSPEND TO RAM" <linux-pm@vger.kernel.org>,
	"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" 
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86/ACPI/State: Optimize C3 entry on AMD CPUs
Date: Tue, 31 Aug 2021 19:14:48 -0700	[thread overview]
Message-ID: <951c4f8f-30ee-77d3-afb7-46e45c84213d@amd.com> (raw)
In-Reply-To: <CAJZ5v0jWX=H=aZ25PzHdH05bRJvtYbGHfyTgH_68k4kfYkZc5A@mail.gmail.com>


On 8/25/21 11:07 AM, Rafael J. Wysocki wrote:
> On Thu, Aug 19, 2021 at 2:43 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
>> AMD CPU which support C3 shares cache. Its not necessary to flush the
>> caches in software before entering C3. This will cause performance drop
>> for the cores which share some caches. ARB_DIS is not used with current
>> AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> Applied as 5.15 material under the edited subject "x86: ACPI: cstate:
> Optimize C3 entry on AMD CPUs", thanks!

I might need to send subsequent patch for this. Can you please point me 
to git and branch where this has been merged.

>> ---
>>   arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
>> index 7de599eba7f0..62a5986d625a 100644
>> --- a/arch/x86/kernel/acpi/cstate.c
>> +++ b/arch/x86/kernel/acpi/cstate.c
>> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>>                   */
>>                  flags->bm_control = 0;
>>          }
>> +       if (c->x86_vendor == X86_VENDOR_AMD) {
>> +               /*
>> +                * For all AMD CPUs that support C3, caches should not be
>> +                * flushed by software while entering C3 type state. Set
>> +                * bm->check to 1 so that kernel doesn't need to execute
>> +                * cache flush operation.
>> +                */
>> +               flags->bm_check = 1;
>> +               /*
>> +                * In current AMD C state implementation ARB_DIS is no longer
>> +                * used. So set bm_control to zero to indicate ARB_DIS is not
>> +                * required while entering C3 type state.
>> +                */
>> +               flags->bm_control = 0;
>> +       }
>>   }
>>   EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>>
>> --
>> 2.25.1
>>

  reply	other threads:[~2021-09-01  2:14 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-19  0:43 Deepak Sharma
2021-08-25 18:07 ` Rafael J. Wysocki
2021-09-01  2:14   ` Deepak Sharma [this message]
2021-09-01 12:45     ` Rafael J. Wysocki
2021-09-22  3:50       ` Sharma, Deepak
2021-09-22 12:47         ` Rafael J. Wysocki
2021-09-24  5:42           ` Sharma, Deepak
2021-08-26 23:04 ` Thomas Gleixner
2021-09-01  2:10   ` Deepak Sharma

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