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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Tom Joseph <tjoseph@cadence.com>, <linux-omap@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Lokesh Vutla <lokeshvutla@ti.com>
Subject: Re: [PATCH v2 2/3] PCI: j721e: Add PCI legacy interrupt support for J721E
Date: Wed, 11 Aug 2021 17:37:19 +0530	[thread overview]
Message-ID: <9638f916-d0da-9c0e-6f01-b90c986decfd@ti.com> (raw)
In-Reply-To: <875ywdbhta.wl-maz@kernel.org>

Hi Marc,

On 10/08/21 6:03 pm, Marc Zyngier wrote:
> On Mon, 09 Aug 2021 15:58:38 +0100,
> Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Hi Marc,
>>
>> On 09/08/21 3:09 pm, Marc Zyngier wrote:
>>> On Mon, 09 Aug 2021 05:50:10 +0100,
>>> Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>>>
>>>> Hi Marc,
>>>>
>>>> On 04/08/21 8:43 pm, Marc Zyngier wrote:
>>>>> On Wed, 04 Aug 2021 14:29:11 +0100,
>>>>> Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>>>>>
>>>>>> Add PCI legacy interrupt support for J721E. J721E has a single HW
>>>>>> interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
>>>>>> The HW interrupt line connected to GIC is a pulse interrupt whereas
>>>>>> the legacy interrupts by definition is level interrupt. In order to
>>>>>> provide level interrupt functionality to edge interrupt line, PCIe
>>>>>> in J721E has provided IRQ_EOI register.
>>>>>>
>>>>>> However due to Errata ID #i2094 ([1]), EOI feature is not enabled in HW
>>>>>> and only a single pulse interrupt will be generated for every
>>>>>> ASSERT_INTx/DEASSERT_INTx.
>>>>>
>>>>> So my earlier remark stands. If you get a single edge, how do you
>>>>> handle a level that is still high after having handled the interrupt
>>>>> on hardware that has this bug?
>>>>
>>>> Right, this hardware (J721E) has a bug but was fixed in J7200 (Patch 3/3
>>>> handles that).
>>>
>>> But how do you make it work with J721E? Is it even worth supporting if
>>> (as I expect) it is unreliable?
>>
>> I've seen at-least the NVMe devices triggers the interrupts again and
>> the data transfer completes. But I agree, this is unreliable.
> 
> Then I don't think you should add INTx support for this system. It is
> bound to be a support burden, and will reflect badly on the whole
> platform. Focusing on J7200 is probably the best thing to do.

Okay, will drop this patch from the series and have INTx support only
for J7200.

Thanks
Kishon

  reply	other threads:[~2021-08-11 12:07 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-04 13:29 [PATCH v2 0/3] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I
2021-08-04 13:29 ` [PATCH v2 1/3] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I
2021-08-04 15:05   ` Marc Zyngier
2021-08-09  4:38     ` Kishon Vijay Abraham I
2021-08-13 17:17   ` Rob Herring
2021-08-18 13:58     ` Kishon Vijay Abraham I
2021-09-23  4:33       ` Kishon Vijay Abraham I
2021-09-23 15:44         ` Rob Herring
2021-08-04 13:29 ` [PATCH v2 2/3] PCI: j721e: Add PCI legacy interrupt support for J721E Kishon Vijay Abraham I
2021-08-04 15:13   ` Marc Zyngier
2021-08-09  4:50     ` Kishon Vijay Abraham I
2021-08-09  9:39       ` Marc Zyngier
2021-08-09 14:58         ` Kishon Vijay Abraham I
2021-08-10 12:33           ` Marc Zyngier
2021-08-11 12:07             ` Kishon Vijay Abraham I [this message]
2021-08-04 13:29 ` [PATCH v2 3/3] PCI: j721e: Add PCI legacy interrupt support for J7200 Kishon Vijay Abraham I

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