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From: Michal Simek <michal.simek@xilinx.com>
To: Linus Walleij <linus.walleij@linaro.org>,
	Piyush Mehta <piyush.mehta@xilinx.com>
Cc: Arnd Bergmann <arnd@arndb.de>, Zou Wei <zou_wei@huawei.com>,
	Greg KH <gregkh@linuxfoundation.org>,
	Michal Simek <michal.simek@xilinx.com>, <wendy.liang@xilinx.com>,
	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,
	"Bartosz Golaszewski" <bgolaszewski@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>, <rajan.vaja@xilinx.com>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>, git <git@xilinx.com>,
	"Srinivas Goud" <sgoud@xilinx.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2 3/3] gpio: modepin: Add driver support for modepin GPIO controller
Date: Wed, 11 Aug 2021 15:29:46 +0200	[thread overview]
Message-ID: <974df9ef-6cdb-cb7b-2b9d-2eddaf1171f7@xilinx.com> (raw)
In-Reply-To: <CACRpkdZ=WRhTTQOvQcDEQhbf5Fone0GHopZfJhsQfsS-NRQUUw@mail.gmail.com>

Hi Linus,

On 8/11/21 2:59 PM, Linus Walleij wrote:
> Hi Piyush,
> 
> thanks for your patch!
> 
> Can you explain one thing to me: since this is now a GPIO driver
> that means "General Purpos Input/Output", then these bits are
> accessed like this:
> 
> On Thu, Aug 5, 2021 at 7:43 PM Piyush Mehta <piyush.mehta@xilinx.com> wrote:
> 
>> +       ret = zynqmp_pm_bootmode_read(&bootpin_val);
> 
> This does not look very general purpose. These seem to be all about
> boot mode, right?
> 
> So can you explain why this should be a GPIO driver at all?
> 
> I understand it is sometimes convenient to describe stuff as GPIO even
> if it is not (for example to get a convenient userspace interface) but
> as maintainers
> we really need to make sure that the subsystem is not being abused
> for things not GPIO.

They are bootmode pins because that pins are designed and used by ROM to
get information which boot device should be used.
But after this is it is really behaving as generic purpose I/O pins.
Xilinx is using them for years for usb phy resets. I have also seen them
to be used for other reset functionality.
And that's exactly what we are trying to do here by this driver. Because
usb hubs/phys have reset normally connected via gpio pin which is
toggled. And we have boards where these resets are connected via these
pins or via hard gpio IP or via i2c-gpio expanders that's why IMHO this
option should be designed in the same way to have gpio reset
functionality added dwc3 and based on DT/board bootmode gpio, ps gpio,
pl gpio, i2c gpio or gpio over power regulators, etc will be used.

Please let me know if you want to get more information about it.

Thanks,
Michal


  reply	other threads:[~2021-08-11 13:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-05 17:42 [PATCH V2 0/3] " Piyush Mehta
2021-08-05 17:42 ` [PATCH V2 1/3] firmware: zynqmp: Add MMIO read and write support for PS_MODE pin Piyush Mehta
2021-08-06  5:49   ` Michal Simek
2021-08-11 13:08   ` Linus Walleij
2021-08-11 13:46     ` Arnd Bergmann
2021-08-11 14:04       ` Michal Simek
2021-08-11 15:14   ` Linus Walleij
2021-08-05 17:42 ` [PATCH V2 2/3] dt-bindings: gpio: zynqmp: Add binding documentation for modepin Piyush Mehta
2021-08-13 19:01   ` Rob Herring
2021-08-16  6:27     ` Michal Simek
2021-08-05 17:42 ` [PATCH V2 3/3] gpio: modepin: Add driver support for modepin GPIO controller Piyush Mehta
2021-08-11 12:59   ` Linus Walleij
2021-08-11 13:29     ` Michal Simek [this message]
2021-08-11 14:45       ` Linus Walleij
2021-08-11 15:12   ` Linus Walleij

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