Re: [PATCH v2 8/9] drm/mediatek: add DSC support for mt8195

Re: [PATCH v2 8/9] drm/mediatek: add DSC support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add DSC module file.

Introduce DSC here.

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 205 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 ++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  7 files changed, 233 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..a1b239135c8f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_gamma.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
> +                 mtk_disp_dsc.o \
>                   mtk_drm_crtc.o \
>                   mtk_drm_ddp_comp.o \
>                   mtk_drm_drv.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..128d9fdbaf9e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -89,4 +89,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
>                             void *vblank_cb_data);
>  void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_dsc_clk_enable(struct device *dev);
> +void mtk_dsc_clk_disable(struct device *dev);
> +void mtk_dsc_config(struct device *dev, unsigned int width,
> +                   unsigned int height, unsigned int vrefresh,
> +                   unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_dsc_start(struct device *dev);
> +void mtk_dsc_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> new file mode 100644
> index 000000000000..61187f824c19
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> @@ -0,0 +1,205 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_gem.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                         BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_IN_SRC_SEL                         BIT(3)
> +#define DSC_BYPASS                                     BIT(4)
> +#define DSC_RELAY                                      BIT(5)
> +#define DSC_EMPTY_FLAG_SEL                     0xc000
> +#define DSC_UFOE_SEL                           BIT(16)
> +#define DISP_REG_DSC_OBUF                      0x0070
> +
> +/**
> + * struct mtk_disp_dsc - DISP_DSC driver structure
> + * @clk - clk of dsc hardware
> + * @regs - hardware register address of dsc
> + * @comp_id - enum type of component id
> + * @cmdq_reg - structure containing cmdq hardware resource
> + */
> +struct mtk_disp_dsc {
> +       struct clk *clk;
> +       void __iomem *regs;
> +       enum mtk_ddp_comp_id comp_id;

comp_id is useless, so remove.

> +       struct cmdq_client_reg          cmdq_reg;
> +};
> +
> +void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +       void __iomem *baddr = dsc->regs;
> +       int ret = 0;
> +
> +       ret = pm_runtime_get_sync(dev);

I think no sub driver enable the power, so sync with other sub driver.

> +       if (ret < 0)
> +               DRM_ERROR("Failed to enable power domain: %d\n", ret);
> +
> +       mtk_ddp_write_mask(NULL, DSC_EN,
> +                          &dsc->cmdq_reg, baddr,
> +                          DISP_REG_DSC_CON, DSC_EN);
> +
> +       pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));

No sub driver print this, sync with other sub driver.

> +}
> +
> +void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +       void __iomem *baddr = dsc->regs;
> +       int ret = 0;
> +
> +       mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> +                          DISP_REG_DSC_CON, DSC_EN);
> +
> +       pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));

Why we need this information?

> +
> +       ret = pm_runtime_put(dev);

Ditto as pm_runtime_get_sync().

> +       if (ret < 0)
> +               DRM_ERROR("Failed to disable power domain: %d\n", ret);
> +}
> +
> +int mtk_dsc_clk_enable(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       return clk_prepare_enable(dsc->clk);
> +}
> +
> +void mtk_dsc_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       clk_disable_unprepare(dsc->clk);
> +}
> +
> +void mtk_dsc_config(struct device *dev, unsigned int w,
> +                   unsigned int h, unsigned int vrefresh,
> +                   unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(handle, DSC_BYPASS,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
> +                            void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
> +                               void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_dsc_component_ops = {
> +       .bind = mtk_disp_dsc_bind,
> +       .unbind = mtk_disp_dsc_unbind,
> +};
> +
> +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_dsc *priv;
> +       enum mtk_ddp_comp_id comp_id;
> +       int irq;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_DSC);
> +       if ((int)comp_id < 0) {
> +               dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> +               return comp_id;
> +       }
> +
> +       priv->comp_id = comp_id;
> +
> +       irq = platform_get_irq(pdev, 0);

Why do you get irq?

> +       if (irq < 0)
> +               return irq;
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get dsc clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap dsc\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       pm_runtime_enable(dev);

Sync with other sub driver.

> +
> +       ret = component_add(dev, &mtk_disp_dsc_component_ops);
> +       if (ret != 0) {
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +               pm_runtime_disable(dev);
> +       }
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> +
> +       pm_runtime_disable(&pdev->dev);

Sync with other sub driver.

> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-dsc", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> +
> +struct platform_driver mtk_disp_dsc_driver = {
> +       .probe = mtk_disp_dsc_probe,
> +       .remove = mtk_disp_dsc_remove,
> +       .driver = {
> +               .name = "mediatek-disp-dsc",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_dsc_driver_dt_match,
> +       },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..d0b0f41dfe5a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
>         .layer_config = mtk_rdma_layer_config,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +       .clk_enable = mtk_dsc_clk_enable,
> +       .clk_disable = mtk_dsc_clk_disable,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -356,6 +364,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_BLS] = "bls",
> +       [MTK_DISP_DSC] = "dsc",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -391,6 +400,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0, &ddp_rdma },
>         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1, &ddp_rdma },
>         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2, &ddp_rdma },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, &ddp_dsc },

Alphabetic order.

>         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
>         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
>         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> @@ -509,6 +521,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_DSC ||

Alphabetic order.

>             type == MTK_DPI ||
>             type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..661fb620e266 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
>         MTK_DISP_BLS,
> +       MTK_DISP_DSC,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d6f6d1bdad85..7dfca63c1042 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt2701-dsi",
> @@ -563,6 +565,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                 if (comp_type == MTK_DISP_CCORR ||
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
> +                   comp_type == MTK_DISP_DSC ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -667,6 +670,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_rdma_driver,
>         &mtk_dpi_driver,
>         &mtk_drm_platform_driver,
> +       &mtk_disp_dsc_driver,

Alphabetic order.

>         &mtk_dsi_driver,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..8b722330ef7d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
> +extern struct platform_driver mtk_disp_dsc_driver;

Alphabetic order.

Regards,
Chun-Kuang.

>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0
>

Re: [PATCH v2 1/9] dt-bindings: mediatek: add definition for mt8195 display

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add definition for mt8195 display.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,disp.txt          | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index fbb59c9ddda6..de6226d4bca3 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
>         "mediatek,<chip>-disp-gamma"            - gamma correction
>         "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> +       "mediatek,<chip>-disp-dsc"              - DSC controller, see mediatek,dsc.yaml

You add dsc binding document in yaml format, so I would like you to
change this binding document to yaml format.

Regards,
Chun-Kuang.

>         "mediatek,<chip>-disp-postmask"         - control round corner for display frame
>         "mediatek,<chip>-disp-split"            - split stream to two encoders
>         "mediatek,<chip>-disp-ufoe"             - data compression engine
> @@ -44,7 +45,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
>         "mediatek,<chip>-disp-mutex"            - display mutex
>         "mediatek,<chip>-disp-od"               - overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
>  - reg: Physical base address and length of the function block register space
>  - interrupts: The interrupt signal from the function block (required, except for
>    merge and split function blocks).
> @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
>         "mediatek,<chip>-disp-ovl"
>         "mediatek,<chip>-disp-rdma"
>         "mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
>  - larb: Should contain a phandle pointing to the local arbiter device as defined
>    in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>  - iommus: Should point to the respective IOMMU block with master port as
> @@ -217,3 +218,7 @@ od@14023000 {
>         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
>         clocks = <&mmsys CLK_MM_DISP_OD>;
>  };
> +
> +dsc0: disp_dsc_wrap@1c009000 {
> +       /* See mediatek,dsc.yaml for details */
> +};
> --
> 2.18.0
>

Re: [PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> The hardware path of vdosys0 with eDP panel output need to go through
> by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
> DITHER, DSC and MERGE.

You should add the difference in each version. [1] is an example for this.

[1] https://patchwork.kernel.org/project/linux-mediatek/cover/20210709022324.1607884-1-eizan@chromium.org/

Regards,
Chun-Kuang.

>
> Add DRM and these modules support by the patches below:
>
> jason-jh.lin (9):
>   dt-bindings: mediatek: add definition for mt8195 display
>   dt-bindings: mediatek: add DSC definition for mt8195
>   dt-bindings: arm: mediatek: add definition for mt8195 mmsys
>   arm64: dts: mt8195: add display node for vdosys0
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
>   drm/mediatek: add DSC support for MT8195
>   drm/mediatek: add MERGE support for MT8195
>
>  .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
>  .../display/mediatek/mediatek,disp.txt        |   9 +-
>  .../display/mediatek/mediatek,dsc.yaml        |  57 ++
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 111 ++++
>  drivers/gpu/drm/mediatek/Makefile             |   2 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  16 +
>  drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 205 +++++++
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 525 ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  14 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  29 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 191 +++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 107 +++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |  10 +
>  18 files changed, 1337 insertions(+), 7 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> --
> 2.18.0
>

Re: [PATCH v2 7/9] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 ++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 24 ++++++++++++++++++++++++
>  2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..d6f6d1bdad85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,

Where is the dp_intf driver in this series?

Regards,
Chun-Kuang.

> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-wdma",
>           .data = (void *)MTK_DISP_WDMA },
>         { .compatible = "mediatek,mt8183-disp-ccorr",
> @@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2701-disp-pwm",
>           .data = (void *)MTK_DISP_BLS },
>         { .compatible = "mediatek,mt8173-disp-pwm",
> @@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Matthias Brugger]

On 10/07/2021 13:38, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-mutex.c | 107 +++++++++++++++++++++++++++++--
>  1 file changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..d74eb3f97f1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
>  #define MT8183_MUTEX0_MOD0			0x30
>  #define MT8183_MUTEX0_SOF0			0x2c
>  
> +#define MT8195_DISP_MUTEX0_MOD0			0x30
> +#define MT8195_DISP_MUTEX0_SOF			0x2c
> +
>  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
>  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
>  #define MT8173_MUTEX_MOD_DISP_PWM1		24
>  #define MT8173_MUTEX_MOD_DISP_OD		25
>  
> +#define MT8195_MUTEX_MOD_DISP_OVL0		0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0		1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0		2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0		3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0		4
> +#define MT8195_MUTEX_MOD_DISP_AAL0		5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0		7
> +#define MT8195_MUTEX_MOD_DISP_DSI0		8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
> +#define MT8195_MUTEX_MOD_DISP_OVL1		10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1		11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1		12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1		13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1		14
> +#define MT8195_MUTEX_MOD_DISP_AAL1		15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1		17
> +#define MT8195_MUTEX_MOD_DISP_DSI1		18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
> +#define MT8195_MUTEX_MOD_DISP_PWM0		27
> +#define MT8195_MUTEX_MOD_DISP_PWM1		28
> +
>  #define MT2712_MUTEX_MOD_DISP_PWM2		10
>  #define MT2712_MUTEX_MOD_DISP_OVL0		11
>  #define MT2712_MUTEX_MOD_DISP_OVL1		12
> @@ -101,11 +134,36 @@
>  #define MT2712_MUTEX_SOF_DSI3			6
>  #define MT8167_MUTEX_SOF_DPI0			2
>  #define MT8167_MUTEX_SOF_DPI1			3
> +
>  #define MT8183_MUTEX_SOF_DSI0			1
>  #define MT8183_MUTEX_SOF_DPI0			2
>  
> -#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
> -#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
> +#define MT8183_MUTEX_EOF_DSI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> +#define MT8183_MUTEX_EOF_DPI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)

Not needed here, please drop.

> +
> +#define MT8195_MUTEX_SOF_DSI0			1
> +#define MT8195_MUTEX_SOF_DSI1			2
> +#define MT8195_MUTEX_SOF_DP_INTF0		3
> +#define MT8195_MUTEX_SOF_DP_INTF1		4
> +#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)

Same here.

Regards,
Matthias

Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Matthias Brugger]

On 10/07/2021 13:38, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-mutex.c | 107 +++++++++++++++++++++++++++++--
>  1 file changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..d74eb3f97f1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
[...]
>  struct mtk_mutex *mtk_mutex_get(struct device *dev)
>  {
>  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +602,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
>  	  .data = &mt8173_mutex_driver_data},
>  	{ .compatible = "mediatek,mt8183-disp-mutex",
>  	  .data = &mt8183_mutex_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-mutex",
> +	  .data = &mt8195_mutex_driver_data},

Are we missing a binding description for that?

Regards,
Matthias

Re: [PATCH v2 1/9] dt-bindings: mediatek: add definition for mt8195 display

[Jason-JH Lin]

On Sun, 2021-07-11 at 09:21 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > Add definition for mt8195 display.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  .../bindings/display/mediatek/mediatek,disp.txt          | 9
> > +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > index fbb59c9ddda6..de6226d4bca3 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > @@ -37,6 +37,7 @@ Required properties (all function blocks):
> >         "mediatek,<chip>-disp-aal"              - adaptive ambient
> > light controller
> >         "mediatek,<chip>-disp-gamma"            - gamma correction
> >         "mediatek,<chip>-disp-merge"            - merge streams
> > from two RDMA sources
> > +       "mediatek,<chip>-disp-dsc"              - DSC controller,
> > see mediatek,dsc.yaml
> 
> You add dsc binding document in yaml format, so I would like you to
> change this binding document to yaml format.
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

OK, I will change this binding document to yaml format at the next
version.

Regards,
Jason-JH.Lin
> >         "mediatek,<chip>-disp-postmask"         - control round
> > corner for display frame
> >         "mediatek,<chip>-disp-split"            - split stream to
> > two encoders
> >         "mediatek,<chip>-disp-ufoe"             - data compression
> > engine
> > @@ -44,7 +45,7 @@ Required properties (all function blocks):
> >         "mediatek,<chip>-dpi"                   - DPI controller,
> > see mediatek,dpi.txt
> >         "mediatek,<chip>-disp-mutex"            - display mutex
> >         "mediatek,<chip>-disp-od"               - overdrive
> > -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183 and mt8192.
> > +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183, mt8192 and mt8195.
> >  - reg: Physical base address and length of the function block
> > register space
> >  - interrupts: The interrupt signal from the function block
> > (required, except for
> >    merge and split function blocks).
> > @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
> >         "mediatek,<chip>-disp-ovl"
> >         "mediatek,<chip>-disp-rdma"
> >         "mediatek,<chip>-disp-wdma"
> > -  the supported chips are mt2701, mt8167 and mt8173.
> > +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
> >  - larb: Should contain a phandle pointing to the local arbiter
> > device as defined
> >    in Documentation/devicetree/bindings/memory-
> > controllers/mediatek,smi-larb.yaml
> >  - iommus: Should point to the respective IOMMU block with master
> > port as
> > @@ -217,3 +218,7 @@ od@14023000 {
> >         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> >         clocks = <&mmsys CLK_MM_DISP_OD>;
> >  };
> > +
> > +dsc0: disp_dsc_wrap@1c009000 {
> > +       /* See mediatek,dsc.yaml for details */
> > +};
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v2 7/9] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Jason-JH Lin]

On Wed, 2021-07-14 at 22:35 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> > driver.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 ++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 24
> > ++++++++++++++++++++++++
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index 728aaadfea8c..00e9827acefe 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data
> > mt8183_rdma_driver_data = {
> >         .fifo_size = 5 * SZ_1K,
> >  };
> > 
> > +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> > +       .fifo_size = 1920,
> > +};
> > +
> >  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] =
> > {
> >         { .compatible = "mediatek,mt2701-disp-rdma",
> >           .data = &mt2701_rdma_driver_data},
> > @@ -362,6 +366,8 @@ static const struct of_device_id
> > mtk_disp_rdma_driver_dt_match[] = {
> >           .data = &mt8173_rdma_driver_data},
> >         { .compatible = "mediatek,mt8183-disp-rdma",
> >           .data = &mt8183_rdma_driver_data},
> > +       { .compatible = "mediatek,mt8195-disp-rdma",
> > +         .data = &mt8195_rdma_driver_data},
> >         {},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..d6f6d1bdad85 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id
> > mt8183_mtk_ddp_ext[] = {
> >         DDP_COMPONENT_DPI0,
> >  };
> > 
> > +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> > +       DDP_COMPONENT_OVL0,
> > +       DDP_COMPONENT_RDMA0,
> > +       DDP_COMPONENT_COLOR0,
> > +       DDP_COMPONENT_CCORR,
> > +       DDP_COMPONENT_AAL0,
> > +       DDP_COMPONENT_GAMMA,
> > +       DDP_COMPONENT_DITHER,
> > +       DDP_COMPONENT_DSC0,
> > +       DDP_COMPONENT_MERGE0,
> > +       DDP_COMPONENT_DP_INTF0,
> 
> Where is the dp_intf driver in this series?
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

dp_intf driver will be upstream in another series patches by DP owner.

Regards,
Jason-JH.Lin

> > +};
> > +
> >  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> >         .main_path = mt2701_mtk_ddp_main,
> >         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> > @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> >  };
> > 
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > +       .main_path = mt8195_mtk_ddp_main,
> > +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> > +};
> > +
> >  static int mtk_drm_kms_init(struct drm_device *drm)
> >  {
> >         struct mtk_drm_private *private = drm->dev_private;
> > @@ -410,6 +428,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_RDMA },
> >         { .compatible = "mediatek,mt8183-disp-rdma",
> >           .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8195-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> >         { .compatible = "mediatek,mt8173-disp-wdma",
> >           .data = (void *)MTK_DISP_WDMA },
> >         { .compatible = "mediatek,mt8183-disp-ccorr",
> > @@ -448,6 +468,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt8183-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> > +       { .compatible = "mediatek,mt8195-disp-mutex",
> > +         .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt2701-disp-pwm",
> >           .data = (void *)MTK_DISP_BLS },
> >         { .compatible = "mediatek,mt8173-disp-pwm",
> > @@ -468,6 +490,8 @@ static const struct of_device_id
> > mtk_drm_of_ids[] = {
> >           .data = &mt8173_mmsys_driver_data},
> >         { .compatible = "mediatek,mt8183-mmsys",
> >           .data = &mt8183_mmsys_driver_data},
> > +       {.compatible = "mediatek,mt8195-vdosys0",
> > +         .data = &mt8195_vdosys0_driver_data},
> >         { }
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

Re: [PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[Jason-JH Lin]

On Sun, 2021-07-11 at 09:24 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > The hardware path of vdosys0 with eDP panel output need to go
> > through
> > by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
> > DITHER, DSC and MERGE.
> 
> You should add the difference in each version. [1] is an example for
> this.
> 
> [1] 
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/cover/20210709022324.1607884-1-eizan@chromium.org/__;!!CTRNKA9wMg0ARbw!1EwjwrNBixHVZwmgU4wIRyVUYiL40xPc64oURf6mVeiJ5j__sO-kMNLyaLBfRc53u9qX$
>  
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

I'll add this at the next version.

Regards,
Jason-JH.Lin
> > 
> > Add DRM and these modules support by the patches below:
> > 
> > jason-jh.lin (9):
> >   dt-bindings: mediatek: add definition for mt8195 display
> >   dt-bindings: mediatek: add DSC definition for mt8195
> >   dt-bindings: arm: mediatek: add definition for mt8195 mmsys
> >   arm64: dts: mt8195: add display node for vdosys0
> >   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> >   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> >   drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
> >   drm/mediatek: add DSC support for MT8195
> >   drm/mediatek: add MERGE support for MT8195
> > 
> >  .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
> >  .../display/mediatek/mediatek,disp.txt        |   9 +-
> >  .../display/mediatek/mediatek,dsc.yaml        |  57 ++
> >  arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 111 ++++
> >  drivers/gpu/drm/mediatek/Makefile             |   2 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  16 +
> >  drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 205 +++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 525
> > ++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  14 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  29 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
> >  drivers/soc/mediatek/mt8195-mmsys.h           | 191 +++++++
> >  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
> >  drivers/soc/mediatek/mtk-mutex.c              | 107 +++-
> >  include/linux/soc/mediatek/mtk-mmsys.h        |  10 +
> >  18 files changed, 1337 insertions(+), 7 deletions(-)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam
> > l
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>