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From: Yinghai Lu <email@example.com>
To: Suresh Siddha <firstname.lastname@example.org>
Cc: "Brown, Len" <email@example.com>,
Thomas Gleixner <firstname.lastname@example.org>,
Ingo Molnar <email@example.com>, "H. Peter Anvin" <firstname.lastname@example.org>,
Pavel Machek <email@example.com>, "Rafael J. Wysocki" <firstname.lastname@example.org>,
ACPI Devel Maling List <email@example.com>
Subject: Re: [PATCH -v2] x86, acpi: Handle xapic/x2apic entries in MADT at same time
Date: Fri, 28 Jan 2011 18:17:53 -0800 [thread overview]
Message-ID: <AANLkTikm=pSoUsyBOF_L-eiw+B631G0fTEwNP7GZ2Gj1@mail.gmail.com> (raw)
On Fri, Jan 28, 2011 at 6:01 PM, Suresh Siddha
> On Thu, 2011-01-27 at 19:09 -0800, Yinghai Lu wrote:
>> One system have mixing xapic and x2apic entries in MADT and SRAT.
>> BIOS guys insist that ACPI 4.0 SPEC said so, if apic id < 255, even
>> the cpus are with x2apic mode pre-enabled, still need to use xapic entries
>> instead of x2apic entries.
> true. thats what the spec says.
I was thinking if cpus are with x2apic pre-enabled, we should have
x2apic entries for them.
>> on 8 socket system with x2apic pre-enabled, will get out of order sequence:
>> CPU0: socket0, core0, thread0.
>> CPU1 - CPU 40: socket 4 - socket 7, thread 0
>> CPU41 - CPU 80: socket 4 - socket 7, thread 1
>> CPU81 - CPU 119: socket 0 - socket 3, thread 0
>> CPU120 - CPU 159: socket 0 - socket 3, thread 1
>> so max_cpus=80 will not get all thread0 now.
>> Need to handle every entry in MADT at same time with xapic and x2apic.
>> so we can honor sequence in MADT.
> hmm few things.
> So is your bios listing like this:
> xapic entries for all thread-0
> x2apic entries for all thread-0
> xapic entries for all thread-1
> x2apic entries for all thread-1
Yes. that is required by BIOS write guide, it says all thread 0 should
> What happens if some other bios lists like:
> all xapic entries
> followed by all x2apic entries
assume should get
CPU0: socket0, core0, thread0.
CPU1 - CPU 80: socket 4 - socket 7, thread 0 and thread 1
CPU81 - CPU 159: socket 0 - socket 3, thread 0 and thread 1
> all x2apic entries
> followed by all x2apic entries
all x2apic ?
> I am not sure if there is a strict recommendation by Intel bios writers
> guide to list all thread-0 first followed by thread-1. Even if there is
> a strict recommendation like that, I am sure there will be some bios's
> that don't follow the rules.
our bios follow the BWG guide.
> Anyways two things.
> a) I don't want to complicate the code too much and still doesn't get
> the desired behavior when some bios has a different silly ordering.
we have right ordering according to ACPI 4.0 spec and BWG
also i think that code is not that complicated.
> b) Also perhaps we need to make it more explicit. Like instead of
> relying on the "maxcpus=n/2" to boot all thread-0's, we should say it
> more explicitly like perhaps nosmt or noht (we used to have this kind of
> option before). Or is it even worth to bother about this, given that we
> can boot all the cpu's and offline the SMT siblings.
interesting, if we have nosmt or noht, we still need to boot that cpu
to use cpuid to
find out thread idx?
next prev parent reply other threads:[~2011-01-29 2:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-28 3:09 Yinghai Lu
2011-01-29 2:01 ` Suresh Siddha
2011-01-29 2:17 ` Yinghai Lu [this message]
2011-01-31 12:24 ` Ingo Molnar
2012-01-31 8:31 Yinghai Lu
2013-01-21 21:39 Yinghai Lu
[not found] ` <CAE9FiQX0bUdWz6bmqLKDHpY5mvjEYdobseroCRnu0-Ju0qmsPw@mail.gmail.com>
[not found] ` <firstname.lastname@example.org>
[not found] ` <CAE9FiQWPiVb_hySAADQypuZtcTN+iEQb4hoO=-+iurdsmKqKrg@mail.gmail.com>
[not found] ` <CAE9FiQUcq05K1mR5E7K-MT3+Z4xxckxO+o9RJ6QDwiGG1T_3aQ@mail.gmail.com>
[not found] ` <CAE9FiQVHcPH3aOU3uD=PsWay1w+csSDzZk62tpMXVgsFVMW1wg@mail.gmail.com>
[not found] ` <CAE9FiQVGZf_cRMK0spp9=YhG8SsrK+FY6fi00pCxZcEL1Neemail@example.com>
[not found] ` <CAE9FiQW6q860P4+qQWTwt0k0vjOJ-S6FdyZHv06=0qv1Z97Cfirstname.lastname@example.org>
2014-08-21 7:00 ` Ingo Molnar
2014-08-21 23:27 ` Yinghai Lu
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