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From: Roland Dreier <roland@purestorage.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Micha Nelissen <micha@neli.hopto.org>,
	Jesse Barnes <jbarnes@virtuousgeek.org>,
	Ingo Molnar <mingo@redhat.com>,
	x86@kernel.org, "Venkatesh Pallipadi (Venki)" <venki@google.com>,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	Matthew Wilcox <matthew@wil.cx>
Subject: Re: [PATCH] Add support for multiple MSI on x86
Date: Wed, 9 Mar 2011 18:05:26 -0800	[thread overview]
Message-ID: <AANLkTinrzY56cwB6OX6xcAb5ZWJcZC5cr-knLkCDPy6p@mail.gmail.com> (raw)
In-Reply-To: <alpine.LFD.2.00.1103082215300.2787@localhost6.localdomain6>

> Yes, but there are MSI devices in the field...

But do any of them benefit from having multiple interrupt vectors available?

If I recall correct, willy was motivated by AHCI performance to try this out,
and in the end things didn't go any faster using multiple MSI.

The big win with multiple interrupt vectors is when you have independent
queues that you can point different CPUs at, and give each CPU its own
interrupt.  And that type of hardware is pretty certain to support MSI-X.

 - R.

  parent reply	other threads:[~2011-03-10  2:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-02-13 20:25 Micha Nelissen
2011-02-14 12:34 ` Ingo Molnar
2011-02-14 19:47   ` Micha Nelissen
2011-02-15  2:38     ` Ingo Molnar
2011-02-14 20:55 ` Thomas Gleixner
2011-03-04 18:37   ` Jesse Barnes
2011-06-17 17:12   ` Matthew Wilcox
2011-03-04 18:36 ` Jesse Barnes
2011-03-04 19:53   ` Micha Nelissen
2011-03-08 21:05     ` Thomas Gleixner
     [not found]       ` <35bd5f56-658b-48e3-a376-b07350a29cf6@email.android.com>
2011-03-08 21:16         ` Thomas Gleixner
     [not found]           ` <71ed11a4-aff7-4eb6-b037-0e097bb96444@email.android.com>
2011-03-08 22:13             ` Thomas Gleixner
2011-03-10  2:05           ` Roland Dreier [this message]
2011-03-10 15:33             ` Clemens Ladisch

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