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From: Stephane Eranian <>
To: Peter Zijlstra <>
Subject: Re: [PATCH 0/2] perf_events: add support for Intel fixed counter 2
Date: Fri, 4 Feb 2011 14:19:13 +0100	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <1296825160.26581.652.camel@laptop>

On Fri, Feb 4, 2011 at 2:12 PM, Peter Zijlstra <> wrote:
> On Fri, 2011-02-04 at 14:00 +0200, Stephane Eranian wrote:
>> This series of patches solves this problem by introducing a custom
>> encoding for UNHALTED_REFERENCE_CYCLES (0xff3c) and improving
>> the constraint infrastructure to handle events which can ONLY be
>> measured on fixed counters.
> Right, so the only problem I can see with this is that Intel will at
> some point in the future put an actual event there.
I doubt that but I will check with them.

The alternative I thought about would be to use a bit in the upper 32
bit section
of attr.config and use the constraint->cmask to catch it. That would
be a special
cmask. That would probably work because ALL events have to go through

  reply	other threads:[~2011-02-04 13:19 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-02-04 12:00 Stephane Eranian
2011-02-04 13:12 ` Peter Zijlstra
2011-02-04 13:19   ` Stephane Eranian [this message]
2011-02-05 15:19     ` Stephane Eranian
2011-02-06 19:55       ` Cyrill Gorcunov

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