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From: "Sanil, Shruthi" <shruthi.sanil@intel.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh@kernel.org>,
	"daniel.lezcano@linaro.org" <daniel.lezcano@linaro.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"andriy.shevchenko@linux.intel.com" 
	<andriy.shevchenko@linux.intel.com>,
	"kris.pan@linux.intel.com" <kris.pan@linux.intel.com>,
	"mgross@linux.intel.com" <mgross@linux.intel.com>,
	"Thokala, Srikanth" <srikanth.thokala@intel.com>,
	"Raja Subramanian,
	Lakshmi Bai"  <lakshmi.bai.raja.subramanian@intel.com>,
	"Sangannavar,
	Mallikarjunappa"  <mallikarjunappa.sangannavar@intel.com>
Subject: RE: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
Date: Thu, 12 Aug 2021 16:49:13 +0000	[thread overview]
Message-ID: <BYAPR11MB3128F143273F060C33DCA9C8F1F99@BYAPR11MB3128.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CAHp75VeAnm-9oy5BinY8DU5tRj0EhU_vVxkvcp0M+wXPSv8Wdw@mail.gmail.com>

> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@gmail.com>
> Sent: Wednesday, August 4, 2021 1:08 PM
> To: Sanil, Shruthi <shruthi.sanil@intel.com>
> Cc: Rob Herring <robh@kernel.org>; daniel.lezcano@linaro.org;
> tglx@linutronix.de; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com;
> kris.pan@linux.intel.com; mgross@linux.intel.com; Thokala, Srikanth
> <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai
> <lakshmi.bai.raja.subramanian@intel.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar@intel.com>
> Subject: Re: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem
> Bay SoC Timer
> 
> On Wed, Aug 4, 2021 at 8:35 AM Sanil, Shruthi <shruthi.sanil@intel.com>
> wrote:
> > > From: Rob Herring <robh@kernel.org>
> > > Sent: Tuesday, August 3, 2021 4:14 AM
> 
> ...
> 
> > > > +properties:
> > >
> > > You need a 'compatible' here. Otherwise, how does one know what 'reg'
> > > contains. Also, without it, this schema will never be applied.
> > >
> >
> > This is a parent block that has the common configuration register address
> defined which we would need during the initialization of the child nodes. This
> block in itself is not doing anything. We have this because, we have a
> common register that is required to be accessed during all the timers and
> counter initialization.
> > The child nodes have the compatible string, which is used in the driver. I
> have validated this on the Keem Bay HW and see that the timer probes are
> being called and the timers are functional as expected.
> 
> I think I understand now. The problem is that the current state of affairs with
> this block is incorrect software representation. What you need is to create an
> MFD device driver (for which the compatible will exactly the one Rob is telling
> about) and from it you register the rest of your drivers. The existing drivers
> for this block should be converted to MFD schema.

Sure Andy, I shall check on this and get back.
Thank You!

> 
> --
> With Best Regards,
> Andy Shevchenko

  reply	other threads:[~2021-08-12 16:49 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-29  5:39 [PATCH v5 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2021-07-29  5:39 ` [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2021-08-02 22:43   ` Rob Herring
2021-08-04  5:25     ` Sanil, Shruthi
2021-08-04  7:38       ` Andy Shevchenko
2021-08-12 16:49         ` Sanil, Shruthi [this message]
2021-08-23  6:02           ` Sanil, Shruthi
2021-07-29  5:39 ` [PATCH v5 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil

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