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Fri, 10 May 2019 18:53:25 +0000 Received: from BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::e843:91f7:56c:73e8]) by BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::e843:91f7:56c:73e8%5]) with mapi id 15.20.1878.019; Fri, 10 May 2019 18:53:25 +0000 From: Sowjanya Komatineni To: Mark Brown CC: "thierry.reding@gmail.com" , Jonathan Hunter , Timo Alho , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "Krishna Yarlagadda" , Laxman Dewangan , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH V3 5/9] spi: export spi core function spi_set_cs Thread-Topic: [PATCH V3 5/9] spi: export spi core function spi_set_cs Thread-Index: AQHU89KFcGFem7n2hUyXzOJxTF1ajaZDnpyAgBAjKRCACeNYgIAHM2Xw Date: Fri, 10 May 2019 18:53:25 +0000 Message-ID: References: <1555363834-32155-1-git-send-email-skomatineni@nvidia.com> <1555363834-32155-6-git-send-email-skomatineni@nvidia.com> <20190419151823.GS2803@sirena.org.uk> <20190506044425.GN14916@sirena.org.uk> In-Reply-To: <20190506044425.GN14916@sirena.org.uk> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=skomatineni@nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557514427; bh=VT8bt+syJmx854wEZloec1bmVexlWZhId+Yw+YOfMPY=; h=X-PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-microsoft-antispam:x-ms-traffictypediagnostic: x-microsoft-antispam-prvs:x-ms-oob-tlc-oobclassifiers: x-forefront-prvs:x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=cFo31SneKSwPX/nIxOFVh3+HocEQxWmSoeob7zEw5wQs3/llIXXvBWa18PkAueJEc tmJEhDXLtPzOi4uCBLKaIoEkA1KgACt6aih3QIIXKelzf45r/ogvMDdimkMDTyEKKu JaVHb0CD15356nkqi8u96RN+yRJKBPS+TVhHsB9BobQl4FF7ZWaTRhT7gRReM3Gm/g sIu+XgC/q9L62ahN1KnADyt+prmxuKjgJ08GKleHe6pNzAESGK8rZK7W5gjj0SbYOu zdii7Y8xsW4NhCCB6ep2C1xLZyWbGaO7m65NBo01MjrjYR9gGQLnGh50ye6qaY33qU zz+w8Sp+8j/Ng== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Mon, Apr 29, 2019 at 10:02:46PM +0000, Sowjanya Komatineni wrote: >=20 > Please fix your mail client to word wrap within paragraphs at something s= ubstantially less than 80 columns. Doing this makes your messages much eas= ier to read and reply to. >=20 > > > On Mon, Apr 15, 2019 at 02:30:30PM -0700, Sowjanya Komatineni wrote: > > > > This patch exports spi_set_cs of the spi core to allow SPI masters= =20 > > > > to use when gpio based chip select is needed. > > > > This isn't really what I meant when I said it'd be good to use the=20 > > > core GPIO code - this function doesn't do a huge amount really and=20 > > > the usage of it in your subsequent patch for the > driver isn't=20 > > > exactly joined up with the little it does (which is mainly swapping=20 > > > in the GPIO chip select instead of the hardware chip select) isn't=20 > > > used in your driver usage of this as far as I can see. The bulk of=20 > > > the chip select handling code in the core is actually in > > > transfer_one_message() which your driver doesn't use as it's got=20 > > > it's own implementation of that; I've not looked in enough detail to= =20 > > > figure out if it could use it. > > > In SPI Tegra driver, we wanted to have GPIO based CS control when=20 > > cs-gpios is specified in parallel to HW/SW CS. Having parallel GPIO=20 > > based CS is to mimic some of the timing stuff that's needed for some=20 > > spi devices by not actually using HW CS on platform but only for SPI=20 > > HW design logic inside the chip. > > > Tegra spi driver don't use set_cs callback so looking into spi_set_cs=20 > > from spi core implementation when cs-gpios property is used it exactly= =20 > > the same that is needed for GPIO control CS. So used this in V3. > > > Can you please provide more details on what you are suggesting? > > Do you prefer not to use SPI core spi_set_cs and gpio_set_values APIs=20 > > and instead implement in tegra SPI driver using GPIO descriptors ? > > You're probably best open coding in the driver if there's value in using = the hardware chip select. Sorry, Just to be clear on my understanding of your suggestion, 3 ways of CS control implementation is needed for Tegra SPI - SW CS thru SPI Controller - HW CS thru SPI Controller - Direct GPIO based CS control=20 Patch Series includes both HW CS and also direct GPIO based CS. Regarding direct GPIO based CS, I understood you prefer to use GPIO descrip= tors. I see SPI core set_cs API also uses GPIO descriptor for direct GPIO control= of CS.=20 Tegra SPI driver need parallel implementation of direct gpio based cs to hw= /sw based CS control thru SPI controller. Since SPI core set_cs already has implementation using gpio descriptors, in= V3 I am using the same API. Any concerns for using set_cs API from SPI core as it already does direct g= pio based cs using Descriptors? Thanks Sowjanya =20