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* [PATCH v5] drm/mediatek: add dither 6 setting
@ 2021-07-20  6:29 Yongqiang Niu
  2021-07-20  6:29 ` Yongqiang Niu
  0 siblings, 1 reply; 3+ messages in thread
From: Yongqiang Niu @ 2021-07-20  6:29 UTC (permalink / raw)
  To: Chun-Kuang Hu
  Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
	Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
	Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
	Hsin-Yi Wang

Change since v4:
- change commit message


Yongqiang Niu (1):
  Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()
    function)

 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
1.8.1.1.dirty


^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH v5] drm/mediatek: add dither 6 setting
  2021-07-20  6:29 [PATCH v5] drm/mediatek: add dither 6 setting Yongqiang Niu
@ 2021-07-20  6:29 ` Yongqiang Niu
  2021-08-02 23:00   ` Chun-Kuang Hu
  0 siblings, 1 reply; 3+ messages in thread
From: Yongqiang Niu @ 2021-07-20  6:29 UTC (permalink / raw)
  To: Chun-Kuang Hu
  Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
	Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
	Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
	Hsin-Yi Wang

dither 6 setting is missed in a6b7c98afdca
bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
bit 2 is rdither_en(Enables running order dithering), need disable

Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common())
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 99cbf44..7dd8e05 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -26,6 +26,7 @@
 #define DISP_OD_CFG				0x0020
 #define DISP_OD_SIZE				0x0030
 #define DISP_DITHER_5				0x0114
+#define DISP_DITHER_6				0x0118
 #define DISP_DITHER_7				0x011c
 #define DISP_DITHER_15				0x013c
 #define DISP_DITHER_16				0x0140
@@ -135,6 +136,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 
 	if (bpc >= MTK_MIN_BPC) {
 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
+		mtk_ddp_write(cmdq_pkt, 0x3002, cmdq_reg, regs, DISP_DITHER_6);
 		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
 		mtk_ddp_write(cmdq_pkt,
 			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
-- 
1.8.1.1.dirty


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH v5] drm/mediatek: add dither 6 setting
  2021-07-20  6:29 ` Yongqiang Niu
@ 2021-08-02 23:00   ` Chun-Kuang Hu
  0 siblings, 0 replies; 3+ messages in thread
From: Chun-Kuang Hu @ 2021-08-02 23:00 UTC (permalink / raw)
  To: Yongqiang Niu
  Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
	David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
	Dennis YC Hsieh, DTML, Linux ARM,
	moderated list:ARM/Mediatek SoC support, linux-kernel,
	DRI Development, Project_Global_Chrome_Upstream_Group,
	Hsin-Yi Wang

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年7月20日 週二 下午2:30寫道：
>
> dither 6 setting is missed in a6b7c98afdca
> bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable
> bit 2 is rdither_en(Enables running order dithering), need disable
>
> Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common())
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 99cbf44..7dd8e05 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -26,6 +26,7 @@
>  #define DISP_OD_CFG                            0x0020
>  #define DISP_OD_SIZE                           0x0030
>  #define DISP_DITHER_5                          0x0114
> +#define DISP_DITHER_6                          0x0118
>  #define DISP_DITHER_7                          0x011c
>  #define DISP_DITHER_15                         0x013c
>  #define DISP_DITHER_16                         0x0140
> @@ -135,6 +136,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
>
>         if (bpc >= MTK_MIN_BPC) {
>                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> +               mtk_ddp_write(cmdq_pkt, 0x3002, cmdq_reg, regs, DISP_DITHER_6);

Symbolized 0x3002. BIT(1) is lfsr_en.

Regards,
Chun-Kuang.

>                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
>                 mtk_ddp_write(cmdq_pkt,
>                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> --
> 1.8.1.1.dirty
>

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-08-02 23:00 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2021-07-20  6:29 [PATCH v5] drm/mediatek: add dither 6 setting Yongqiang Niu
2021-07-20  6:29 ` Yongqiang Niu
2021-08-02 23:00   ` Chun-Kuang Hu

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