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From: Joel Stanley <>
To: Florent Kermarrec <>
Cc: "Gabriel L. Somlo" <>,
	"David S . Miller" <>,
	Jakub Kicinski <>,
	Rob Herring <>,
	Stafford Horne <>,
	Benjamin Herrenschmidt <>,
	Anton Blanchard <>, David Shah <>,
	Karol Gugala <>,
	Mateusz Holenko <>,
	devicetree <>,
	Networking <>,
	Linux Kernel Mailing List <>
Subject: Re: [PATCH 2/2] net: Add driver for LiteX's LiteETH network interface
Date: Fri, 20 Aug 2021 07:46:27 +0000	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Hi Florent and Gabriel,

On Fri, 6 Aug 2021 at 12:27, Florent Kermarrec <> wrote:
> Hi Gabriel, Joel,
> for 1), the polling mode has been useful recently with Linux-On-LiteX-Vexriscv to bring up the SMP version before enabling the IRQs and can probably be useful in the future for similar purposes. So if it's not too complicated to maintain, this could be useful to keep it.

I would prefer to get a basic working driver for the straight forward
Linux-on-FPGA use case merged first. We can then work out what should
be done next. I would like to see hardware improvements to make it go
faster, and we can look at other features like polling if you still
need them.

> Le ven. 6 août 2021 à 13:48, Gabriel L. Somlo <> a écrit :
>> Hi Joel,
>> Thanks for pushing this upstream (and for writing it to begin with)!
>> Would you mind diff-ing your version of litex_liteeth.c against what
>> is currently in
>> ?
>> Two main differences we should discuss:
>>         1. there's a polling mode (added by Antony Pavlov), and if we
>>            decide *not* to keep it around, I want to ensure we do that
>>            deliberately, with an explanation as to why;

I assumed this was only for broken systems, or systems that were still
being brought up. Haven't the risc-v socs improved to the point where
they have working interrupts now?

>>         2. LiteX CSRs are accessed using `litex_[read|write][8|16|32]()`
>>            as opposed to simply `[read|write][b|w|l]()`. The former set
>>            are defined in `include/linux/litex.h` and are needed to
>>            ensure correct accesses regardless of endianness, since by
>>            default LiteX registers' endianness mirrors that of the
>>            configured CPU.

I don't like that they get the parameters in the wrong order compared
to the rest of the kernel, and that they force 32-bit access no matter
the width of the access being performed. They also mean we can't use
_releaxed variants of accessors to eg. read a set of registers without
having a barrier in between.

That said, I have used the csr accessors so we can support the mor1k,
which afaict is the only litex CPU that defaults to big endian.

If you could help review the patch so we can get it merged this cycle,
then we can work on future enhancements.



  parent reply	other threads:[~2021-08-20  7:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-06  5:49 [PATCH 0/2] net: Add LiteETH network driver Joel Stanley
2021-08-06  5:49 ` [PATCH 1/2] dt-bindings: net: Add bindings for LiteETH Joel Stanley
2021-08-06 17:07   ` Rob Herring
2021-08-07 19:05   ` Andrew Lunn
2021-08-09  7:59     ` Joel Stanley
2021-08-09 13:27       ` Andrew Lunn
2021-08-06  5:49 ` [PATCH 2/2] net: Add driver for LiteX's LiteETH network interface Joel Stanley
2021-08-06 11:48   ` Gabriel L. Somlo
     [not found]     ` <>
2021-08-20  7:46       ` Joel Stanley [this message]
2021-08-06 23:10   ` Jakub Kicinski
2021-08-09 12:03     ` Joel Stanley
2021-08-09 16:16       ` Jakub Kicinski
2021-08-07 19:19   ` Andrew Lunn
2021-08-09  3:20     ` Joel Stanley
2021-08-09 13:09       ` Andrew Lunn

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