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From: Linus Walleij <linus.walleij@linaro.org>
To: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	linux-stm32@st-md-mailman.stormreply.com,
	Lina Iyer <ilina@codeaurora.org>
Subject: Re: [PATCH] pinctrl: stm32: add lock mechanism for irqmux selection
Date: Fri, 24 May 2019 17:22:09 +0200	[thread overview]
Message-ID: <CACRpkdbJKAGyeBU1tX77-wSYzGXDBqRYR1gQyzOZ_XT4RGFbsw@mail.gmail.com> (raw)
In-Reply-To: <ae00fd9c-d25e-c401-4d21-d526a63538f2@st.com>

On Fri, May 24, 2019 at 2:27 PM Alexandre Torgue
<alexandre.torgue@st.com> wrote:
> On 5/24/19 1:26 PM, Linus Walleij wrote:

> > Patch applied, can't say I fully understand it but you know what
> > you're doing!
>
> Thanks :). Do you need a better explanation ?

What I need to understand for hierarchical interrupt controllers
on GPIO is what I can pull into the gpio library. I am working
to extract some code from drivers/gpio/gpio-ixp4xx.c
to make generic simple hierarchical domain support available,
and Lina is working on generalizing some stuff.

But these complex domain operations in the STM32 seem
to be some special beast.

Yours,
Linus Walleij

      reply	other threads:[~2019-05-24 15:22 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-10  7:43 Alexandre Torgue
2019-05-24 11:26 ` Linus Walleij
2019-05-24 12:27   ` Alexandre Torgue
2019-05-24 15:22     ` Linus Walleij [this message]

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