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[209.85.222.44]) by smtp.gmail.com with ESMTPSA id b77sm11354014vka.21.2018.11.05.08.52.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Nov 2018 08:52:54 -0800 (PST) Received: by mail-ua1-f44.google.com with SMTP id z11so1505943uaa.10 for ; Mon, 05 Nov 2018 08:52:54 -0800 (PST) X-Received: by 2002:a9f:3829:: with SMTP id p38mr10470451uad.25.1541436773650; Mon, 05 Nov 2018 08:52:53 -0800 (PST) MIME-Version: 1.0 References: <20181026173544.136037-1-evgreen@chromium.org> <20181026173544.136037-2-evgreen@chromium.org> <154129921872.88331.15831802252403117971@swboyd.mtv.corp.google.com> In-Reply-To: <154129921872.88331.15831802252403117971@swboyd.mtv.corp.google.com> From: Doug Anderson Date: Mon, 5 Nov 2018 08:52:39 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification To: Stephen Boyd Cc: Andy Gross , Evan Green , Kishon Vijay Abraham I , Rob Herring , devicetree@vger.kernel.org, cang@codeaurora.org, LKML , Manu Gautam , Mark Rutland , Rob Herring Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Sat, Nov 3, 2018 at 7:40 PM Stephen Boyd wrote: > > Quoting Evan Green (2018-10-26 10:35:40) > > (or) > > @@ -150,3 +153,54 @@ Example: > > ... > > ... > > }; > > + > > + phy@88eb000 { > > + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; > > + reg = <0x88eb000 0x18c>; > > + #clock-cells = <1>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, > > + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > > + <&gcc GCC_USB3_SEC_CLKREF_CLK>, > > + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; > > + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; > > + > > + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, > > + <&gcc GCC_USB3_PHY_SEC_BCR>; > > + reset-names = "phy", "common"; > > + > > + lane@88eb200 { > > + reg = <0x88eb200 0x128>, > > + <0x88eb400 0x1fc>, > > + <0x88eb800 0x218>, > > + <0x88eb600 0x70>; > > + #phy-cells = <0>; > > + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; > > + clock-names = "pipe0"; > > + clock-output-names = "usb3_uni_phy_pipe_clk_src"; > > If this has clock-output-names then I would expect to see a #clock-cells > property, but that isn't here in this node. Are we relying on the same > property in the parent node? If I had to guess, I believe it's yet more confusing than that. I believe you actually point to the parent phandle if you want to use the clock. I notice that the parent has #clock-cells as 1 so presumably this is how you point to one child or the other? ...but I don't think it's documented how this works. The lane nodes don't have any sort of ID as far as I can tell. ...and in any case having #clock-cells of 1 makes no sense for USB 3 PHYs which are supposed to only have one child? Let's look at the code, maybe? Hrm, phy_pipe_clk_register() takes no ID or anything. Huh? OK, so as far as I can tell of_clk_add_provider() is never called on this clock... So I think the answer is that #clock-cells should be <0> and should move to the child node to match with clock-output-names. Then I guess (if anyone references this clock from the device tree rather than relying on the global clock-output-names) we should add the of_clk_add_provider() into the code? Maybe we can add that as a patch to the end of this series? There are so many crazy / random things wrong with these bindings that it makes sense to make smaller / incremental changes? -Doug