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Mon, 26 Jul 2021 19:36:15 -0400 Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE501C061764 for ; Mon, 26 Jul 2021 17:16:42 -0700 (PDT) Received: by mail-ot1-x32b.google.com with SMTP id 48-20020a9d0bb30000b02904cd671b911bso11819383oth.1 for ; Mon, 26 Jul 2021 17:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:in-reply-to:references:from:user-agent:date:message-id :subject:to:cc; bh=tscrZBQstzzRaUL+UaPR6i4OEaBy+HrQhXGyWhtHbpY=; b=I0bCa3Idkeu+p5K2AETrjGGnbJVU0B3Kdkogh8ZnX/Pg35bJ5u63zp1PpsZR4PUA71 pJvXM4Jz0xpHXLWmGg5smlJmSgXTQ1IRM4qgno2YoYyOBJ3LpB2LlPz6s+v/qRrjOvKD hKDJtkmccFTnmNWnT0gIloYTbnGn5VN8AvSdQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from :user-agent:date:message-id:subject:to:cc; bh=tscrZBQstzzRaUL+UaPR6i4OEaBy+HrQhXGyWhtHbpY=; b=ovElY/DpQxjRMVuvnOa4KQFUykmcigJ0TJwrh0nJcoXPyuHgAis2RP6mu+Ktonk0Is GIADR7f31hZ3K6aZe3GZv5mAj08iwMru+tB6A7tOQkfGalnx03vpF4lGQBGATXrvDM2B mASxn2ckLJN1mvgTQA8H1zV2ruM1ZyJDufk4U7cgnRV1eJmF+WVTNG6FzlvnNH88alZq xQBKLxaTxV+hPFUhPxHueprJ33nI3Ctor03jxvNhuLeZ9gAOAAoyYB/MuZwjrTkBL2Ot CDz0tH0FSGV/FVMqDpi33lyJi0GriYgomz+ETpyMSrblLr4mYO7Y7StH8xjAYNVD+TFG xeqA== X-Gm-Message-State: AOAM5338kNWc2Ei02FmwIw8tWcpWomYQVdUVtx0wQnqD43wko8vVhm3e uBSLBmgDjy4kkBiUmsRPgBd4ZZyX7IAhkw6VmiJ/HQ== X-Google-Smtp-Source: ABdhPJz9DOthLfEXyaAywpN2zjLbyg7yP79QdEbJyK44iOYpg3YyBnI1HZX1Oyg1Cv6KyXuESXsA/iFNxu6OmeFGo9c= X-Received: by 2002:a9d:650e:: with SMTP id i14mr13685660otl.233.1627345002305; Mon, 26 Jul 2021 17:16:42 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Mon, 26 Jul 2021 20:16:41 -0400 MIME-Version: 1.0 In-Reply-To: <1627147740-11590-1-git-send-email-akhilpo@codeaurora.org> References: <1627147740-11590-1-git-send-email-akhilpo@codeaurora.org> From: Stephen Boyd User-Agent: alot/0.9.1 Date: Mon, 26 Jul 2021 20:16:41 -0400 Message-ID: Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add gpu support To: Akhil P Oommen , Bjorn Andersson , OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS , Rob Herring , dri-devel@lists.freedesktop.org, freedreno , linux-arm-msm@vger.kernel.org Cc: Jonathan Marek , Douglas Anderson , Jordan Crouse , Matthias Kaehlcke , Rob Clark , Andy Gross , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Akhil P Oommen (2021-07-24 10:29:00) > Add the necessary dt nodes for gpu support in sc7280. > > Signed-off-by: Akhil P Oommen > --- > This patch has dependency on the GPUCC bindings patch here: > https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-tdas@codeaurora.org/ To avoid the dependency the plain numbers can be used. > > Changes in v2: > - formatting update and removed a duplicate header (Stephan) > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 116 +++++++++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 029723a..524a5e0 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -585,6 +586,121 @@ > #clock-cells = <1>; > }; > > + gpu@3d00000 { > + compatible = "qcom,adreno-635.0", "qcom,adreno"; > + #stream-id-cells = <16>; > + reg = <0 0x03d00000 0 0x40000>, > + <0 0x03d9e000 0 0x1000>, > + <0 0x03d61000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; > + interrupts = ; > + iommus = <&adreno_smmu 0 0x401>; > + operating-points-v2 = <&gpu_opp_table>; > + qcom,gmu = <&gmu>; > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "gfx-mem"; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-550000000 { > + opp-hz = /bits/ 64 <550000000>; > + opp-level = ; > + opp-peak-kBps = <6832000>; > + }; > + > + opp-450000000 { > + opp-hz = /bits/ 64 <450000000>; > + opp-level = ; > + opp-peak-kBps = <4068000>; > + }; > + > + opp-315000000 { > + opp-hz = /bits/ 64 <315000000>; > + opp-level = ; > + opp-peak-kBps = <1804000>; > + }; > + }; > + }; > + > + gmu: gmu@3d69000 { > + compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; > + reg = <0 0x03d6a000 0 0x34000>, > + <0 0x3de0000 0 0x10000>, > + <0 0x0b290000 0 0x10000>; > + reg-names = "gmu", "rscc", "gmu_pdc"; > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "gmu", > + "cxo", > + "axi", > + "memnoc", > + "ahb", > + "hub", > + "smmu_vote"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>, > + <&gpucc GPU_CC_GX_GDSC>; > + power-domain-names = "cx", > + "gx"; > + iommus = <&adreno_smmu 5 0x400>; > + operating-points-v2 = <&gmu_opp_table>; > + > + gmu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-level = ; > + }; > + }; > + }; > + > + adreno_smmu: iommu@3da0000 { > + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; > + reg = <0 0x03da0000 0 0x20000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, > + <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HUB_AON_CLK>; > + clock-names = "gcc_gpu_memnoc_gfx_clk", > + "gcc_gpu_snoc_dvm_gfx_clk", > + "gpu_cc_ahb_clk", > + "gpu_cc_hlos1_vote_gpu_smmu_clk", > + "gpu_cc_cx_gmu_clk", > + "gpu_cc_hub_cx_int_clk", > + "gpu_cc_hub_aon_clk"; > + > + power-domains = <&gpucc GPU_CC_CX_GDSC>; > + }; > + > lpass_ag_noc: interconnect@3c40000 { This node is 3c40000 and the one above is 3da0000. 3c comes before 3d. Please order nodes properly. > reg = <0 0x03c40000 0 0xf080>; > compatible = "qcom,sc7280-lpass-ag-noc";