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From: Stephen Boyd <swboyd@chromium.org>
To: Linus Walleij <linus.walleij@linaro.org>, skakit@codeaurora.org
Cc: Rob Herring <robh+dt@kernel.org>, Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	David Collins <collinsd@codeaurora.org>,
	Kiran Gunda <kgunda@codeaurora.org>,
	linux-gpio@vger.kernel.org,
	linux-kernel <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 1/2] pinctrl: qcom: spmi-gpio: correct parent irqspec translation
Date: Mon, 16 Aug 2021 14:08:11 -0700	[thread overview]
Message-ID: <CAE-0n53sR12fEa_cNPeT5eGcQVzzL57pd-tYnJbpP0NXkHMTsw@mail.gmail.com> (raw)
In-Reply-To: <4af8171aefd6f0387438225666ec1ccc@codeaurora.org>

Quoting skakit@codeaurora.org (2021-08-15 23:50:37)
> Hi Linus,
>
> On 2021-08-13 14:27, Linus Walleij wrote:
> > Hi Satya/David,
> >
> > nice work on identifying this bug!
> >
> > On Fri, Aug 13, 2021 at 6:56 AM satya priya <skakit@codeaurora.org>
> > wrote:
> >>
> >> From: David Collins <collinsd@codeaurora.org>
> >>
> >> pmic_gpio_child_to_parent_hwirq() and
> >> gpiochip_populate_parent_fwspec_fourcell() translate a pinctrl-
> >> spmi-gpio irqspec to an SPMI controller irqspec.  When they do
> >> this, they use a fixed SPMI slave ID of 0 and a fixed GPIO
> >> peripheral offset of 0xC0 (corresponding to SPMI address 0xC000).
> >> This translation results in an incorrect irqspec for secondary
> >> PMICs that don't have a slave ID of 0 as well as for PMIC chips
> >> which have GPIO peripherals located at a base address other than
> >> 0xC000.
> >>
> >> Correct this issue by passing the slave ID of the pinctrl-spmi-
> >> gpio device's parent in the SPMI controller irqspec and by
> >> calculating the peripheral ID base from the device tree 'reg'
> >> property of the pinctrl-spmi-gpio device.
> >>
> >> Signed-off-by: David Collins <collinsd@codeaurora.org>
> >> Signed-off-by: satya priya <skakit@codeaurora.org>

Can you please add an appropriate Fixes tag?

> >
> > Is this a regression or is it fine if I just apply it for v5.15?
> > I was thinking v5.15 since it isn't yet used in device trees.
> >
>
> Without this fix, [2/2] Vol+ support is failing. If possible please
> merge it on current branch.
>

Are there any boards supported upstream that have a gpio block that
isn't at 0xc000?

  reply	other threads:[~2021-08-16 21:08 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-13  4:55 [PATCH 0/2] Add Vol+ support for sc7280-idp satya priya
2021-08-13  4:55 ` [PATCH 1/2] pinctrl: qcom: spmi-gpio: correct parent irqspec translation satya priya
2021-08-13  8:57   ` Linus Walleij
2021-08-16  6:50     ` skakit
2021-08-16 21:08       ` Stephen Boyd [this message]
2021-08-17  9:06         ` skakit
2021-08-17 19:15           ` Stephen Boyd
2021-08-18  5:26             ` skakit
2021-09-02  3:37               ` Stephen Boyd
2021-08-13  4:55 ` [PATCH 2/2] arm64: dts: sc7280: Add volume up support for sc7280-idp satya priya

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