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bh=T3sN8SO1ZSQjsuFAqVVsec48xDvFtRvQ6c9q1xtJ3w4=; b=Uhx61XsTWkQRSWDKGQfClNv8AJFlW2G3ltbRti5aobXjlUNuiGGolGDhJ7VuqXudwW 8rbQ4yINiyTn9/kgShJ9h4pSUNIcTZkd+nLU8C+jQnY6IcWRTApEUoUVRx28KNylxL4t 7XgrNMN8mRBn87R/KaFrHP/quFbpmWQwOGos/gQQi5qLUKYfC+9tbHUJi23NXuaBtElC R7yrdSrwGkCvS3c/wVdYiyjFH1Yc4CcYZ5upgeE4TdhLKY1LpkkTLCZ1iIOJ05cM9xnc 5BIoRWQ6khh+bVbaszZoo0wSNTnQBWpTFubekkx7fyCmMTpkRWsF1tYL2MSZU4jBPkfv BDMQ== X-Gm-Message-State: APjAAAXWZYGJMh79kbW6NfkJ9+a67iprTslifoCoibU8WX7F4Od4VtVB GGS1EMata/N77x8x2VyMJVwE3SMyWydoqLKPNhY= X-Google-Smtp-Source: APXvYqy40tI6CvvJ9asRzi0J3aqGJnWcjTMCkhuG9+1jRIWgNreuoQSJwZ9k2J7IVuWIgjwmnWP5fdhI9nrccQxCYFo= X-Received: by 2002:a9d:6759:: with SMTP id w25mr10864829otm.348.1557594403820; Sat, 11 May 2019 10:06:43 -0700 (PDT) MIME-Version: 1.0 References: <20190510164940.13496-1-jbrunet@baylibre.com> <20190510164940.13496-3-jbrunet@baylibre.com> In-Reply-To: <20190510164940.13496-3-jbrunet@baylibre.com> From: Martin Blumenstingl Date: Sat, 11 May 2019 19:06:32 +0200 Message-ID: Subject: Re: [PATCH 2/5] arm64: dts: meson: g12a: add ethernet pinctrl definitions To: Jerome Brunet Cc: Kevin Hilman , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jerome, On Fri, May 10, 2019 at 6:49 PM Jerome Brunet wrote: > > Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds > > Signed-off-by: Jerome Brunet > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 37 +++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index a32db09809f7..fe0f73730525 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -206,6 +206,43 @@ > }; > }; > > + eth_leds_pins: eth-leds { > + mux { > + groups = "eth_link_led", > + "eth_act_led"; > + function = "eth"; > + bias-disable; > + }; > + }; > + > + eth_rmii_pins: eth-rmii { > + mux { > + groups = "eth_mdio", > + "eth_mdc", > + "eth_rgmii_rx_clk", > + "eth_rx_dv", > + "eth_rxd0", > + "eth_rxd1", > + "eth_txen", > + "eth_txd0", > + "eth_txd1"; > + function = "eth"; > + bias-disable; > + }; > + }; > + > + eth_rgmii_pins: eth-rgmii { > + mux { > + groups = "eth_rxd2_rgmii", > + "eth_rxd3_rgmii", > + "eth_rgmii_tx_clk", > + "eth_txd2_rgmii", > + "eth_txd3_rgmii"; > + function = "eth"; > + bias-disable; > + }; > + }; it seems that the group definition is incomplete (missing things like eth_mdc, eth_rx_dv, ...) we could also mix the eth_rmii_pins and eth_rgmii_pins in a board.dts (maybe that was your idea in the first place?): phy-mode = "rgmii"; pinctrl-0 = <ð_rmii_pins>, <ð_rgmii_pins>; pinctrl-names = "default"; however, in this case I would prefer if "eth_rmii_pins" was named only "eth_pins" (following mostly what Amlogic does with the pin group naming: eth_* for pins that are valid in both, rmii and rgmii mode and eth*rgmii* for pins that are only valid in rgmii mode) Regards Martin