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From: Billy Laws <blaws05@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: thierry.reding@gmail.com, jonathanh@nvidia.com,
	Laxman Dewangan <ldewangan@nvidia.com>,
	broonie@kernel.org, natechancellor@gmail.com,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-spi@vger.kernel.org
Subject: Re: [PATCH V1 00/12] LP0 entry and exit support for Tegra210
Date: Tue, 28 May 2019 10:28:48 +0100	[thread overview]
Message-ID: <CAFUUQHP5e=oQZC29foYD+uA96r5-M4wCxKYVL_LodrWRG5kp1Q@mail.gmail.com> (raw)
In-Reply-To: <0418cbdb-1bb6-23c3-f13d-e0a70f899f3c@nvidia.com>

Hi,
By the looks of this you configure wake events but the pmc driver
still only configures lp1, which is the same as linux 4 tegra 4.4+
which also doesn't support lp0, if its selected in dts it'll just
change it to LP1/SC7 (both have same code path and neither set any lp0
stuff trm says). What confuses me further is that l4t and this
ptachset both configure wake events, which I think should only work in
LP0 and not LP1 and yet neither have lp0 entry code for t210. I also
looked at ATF, whis sets the flags to wake the cpu on interrupts,
which would suggest that it only supports lp1 (in deep sleep I dont
think them flags would work). Am I missing some important detail here?
Two other things, will you be adding full lp0 in later patchets and
will they use the bpmp or not?

  reply	other threads:[~2019-05-28  9:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-23  1:28 Sowjanya Komatineni
2019-05-23  1:29 ` Sowjanya Komatineni
2019-05-28  9:28   ` Billy Laws [this message]
  -- strict thread matches above, loose matches on Subject: below --
2019-05-21 23:31 Sowjanya Komatineni
2019-05-22 13:33 ` Thierry Reding

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