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* [PATCH] x86/asm: Pin sensitive CR4 bits
@ 2019-02-20  0:54 Kees Cook
  2019-02-20  2:37 ` Jann Horn
  2019-02-20  8:14 ` Dominik Brodowski
  0 siblings, 2 replies; 5+ messages in thread
From: Kees Cook @ 2019-02-20  0:54 UTC (permalink / raw)
  To: Thomas Gleixner; +Cc: linux-kernel, kernel-hardening, x86

Several recent exploits have used direct calls to the native_write_cr4()
function to disable SMEP and SMAP before then continuing their exploits
using userspace memory access. This pins bits of cr4 so that they cannot
be changed through a common function. This is not intended to be general
ROP protection (which would require CFI to defend against properly), but
rather a way to avoid trivial direct function calling (or CFI bypassing
via a matching function prototype) as seen in:

https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-packet.html
(https://github.com/xairy/kernel-exploits/tree/master/CVE-2017-7308)

The goals of this change:
 - pin specific bits (SMEP, SMAP, and UMIP) when writing cr4.
 - avoid setting the bits too early (they must become pinned only after
   first being used).
 - pinning mask needs to be read-only during normal runtime.
 - pinning needs to be rechecked after set to avoid jumps into the middle
   of the function.

Using __ro_after_init on the mask is done so it can't be first disabled
with a malicious write. And since it becomes read-only, we must avoid
writing to it later (hence the check for bits already having been set
instead of unconditionally writing to the mask).

The use of volatile is done to force the compiler to perform a full reload
of the mask after setting cr4 (to protect against just jumping into the
function past where the masking happens; we must check that the mask was
applied after we do the set). Due to how this function can be built by the
compiler (especially due to the removal of frame pointers), jumping into
the middle of the function frequently doesn't require stack manipulation
to construct a stack frame (there may only a retq without pops, which is
sufficient for use with exploits like timer overwrites mentioned above).

For example, without the recheck, the function may appear as:

   native_write_cr4:
      mov [pin], %rbx
      or  %rbx, %rdi
   1: mov %rdi, %cr4
      retq

The masking "or" could be trivially bypassed by just calling to label "1"
instead of "native_write_cr4". (CFI will force calls to only be able to
call into native_write_cr4, but CFI and CET are uncommon currently.)

Signed-off-by: Kees Cook <keescook@chromium.org>
---
 arch/x86/include/asm/special_insns.h | 12 ++++++++++++
 arch/x86/kernel/cpu/common.c         | 12 +++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 43c029cdc3fe..bb08b731a33b 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -72,9 +72,21 @@ static inline unsigned long native_read_cr4(void)
 	return val;
 }
 
+extern volatile unsigned long cr4_pin;
+
 static inline void native_write_cr4(unsigned long val)
 {
+again:
+	val |= cr4_pin;
 	asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
+	/*
+	 * If the MOV above was used directly as a ROP gadget we can
+	 * notice the lack of pinned bits in "val" and start the function
+	 * from the beginning to gain the cr4_pin bits for sure.
+	 */
+	if (WARN_ONCE(cr4_pin && (val & cr4_pin) == 0,
+		      "cr4 pin bypass attempt?!\n"))
+		goto again;
 }
 
 #ifdef CONFIG_X86_64
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cb28e98a0659..7e0ea4470f8e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -312,10 +312,16 @@ static __init int setup_disable_smep(char *arg)
 }
 __setup("nosmep", setup_disable_smep);
 
+volatile unsigned long cr4_pin __ro_after_init;
+EXPORT_SYMBOL_GPL(cr4_pin);
+
 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
 {
-	if (cpu_has(c, X86_FEATURE_SMEP))
+	if (cpu_has(c, X86_FEATURE_SMEP)) {
+		if (!(cr4_pin & X86_CR4_SMEP))
+			cr4_pin |= X86_CR4_SMEP;
 		cr4_set_bits(X86_CR4_SMEP);
+	}
 }
 
 static __init int setup_disable_smap(char *arg)
@@ -334,6 +340,8 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
 
 	if (cpu_has(c, X86_FEATURE_SMAP)) {
 #ifdef CONFIG_X86_SMAP
+		if (!(cr4_pin & X86_CR4_SMAP))
+			cr4_pin |= X86_CR4_SMAP;
 		cr4_set_bits(X86_CR4_SMAP);
 #else
 		cr4_clear_bits(X86_CR4_SMAP);
@@ -351,6 +359,8 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c)
 	if (!cpu_has(c, X86_FEATURE_UMIP))
 		goto out;
 
+	if (!(cr4_pin & X86_CR4_UMIP))
+		cr4_pin |= X86_CR4_UMIP;
 	cr4_set_bits(X86_CR4_UMIP);
 
 	pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
-- 
2.17.1


-- 
Kees Cook

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] x86/asm: Pin sensitive CR4 bits
  2019-02-20  0:54 [PATCH] x86/asm: Pin sensitive CR4 bits Kees Cook
@ 2019-02-20  2:37 ` Jann Horn
  2019-02-20 17:00   ` Kees Cook
  2019-02-20  8:14 ` Dominik Brodowski
  1 sibling, 1 reply; 5+ messages in thread
From: Jann Horn @ 2019-02-20  2:37 UTC (permalink / raw)
  To: Kees Cook
  Cc: Thomas Gleixner, kernel list, Kernel Hardening, the arch/x86 maintainers

On Wed, Feb 20, 2019 at 1:55 AM Kees Cook <keescook@chromium.org> wrote:
> Several recent exploits have used direct calls to the native_write_cr4()
> function to disable SMEP and SMAP before then continuing their exploits
> using userspace memory access. This pins bits of cr4 so that they cannot
> be changed through a common function. This is not intended to be general
> ROP protection (which would require CFI to defend against properly), but
> rather a way to avoid trivial direct function calling (or CFI bypassing
> via a matching function prototype) as seen in:
>
> https://googleprojectzero.blogspot.com/2017/05/exploiting-linux-kernel-via-packet.html
> (https://github.com/xairy/kernel-exploits/tree/master/CVE-2017-7308)
>
> The goals of this change:
>  - pin specific bits (SMEP, SMAP, and UMIP) when writing cr4.
>  - avoid setting the bits too early (they must become pinned only after
>    first being used).
>  - pinning mask needs to be read-only during normal runtime.
>  - pinning needs to be rechecked after set to avoid jumps into the middle
>    of the function.
>
> Using __ro_after_init on the mask is done so it can't be first disabled
> with a malicious write. And since it becomes read-only, we must avoid
> writing to it later (hence the check for bits already having been set
> instead of unconditionally writing to the mask).
>
> The use of volatile is done to force the compiler to perform a full reload
> of the mask after setting cr4 (to protect against just jumping into the
> function past where the masking happens; we must check that the mask was
> applied after we do the set). Due to how this function can be built by the
> compiler (especially due to the removal of frame pointers), jumping into
> the middle of the function frequently doesn't require stack manipulation
> to construct a stack frame (there may only a retq without pops, which is
> sufficient for use with exploits like timer overwrites mentioned above).
>
> For example, without the recheck, the function may appear as:
>
>    native_write_cr4:
>       mov [pin], %rbx
>       or  %rbx, %rdi
>    1: mov %rdi, %cr4
>       retq
>
> The masking "or" could be trivially bypassed by just calling to label "1"
> instead of "native_write_cr4". (CFI will force calls to only be able to
> call into native_write_cr4, but CFI and CET are uncommon currently.)
>
> Signed-off-by: Kees Cook <keescook@chromium.org>
> ---
[...]
>  static inline void native_write_cr4(unsigned long val)
>  {
> +again:
> +       val |= cr4_pin;
>         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
> +       /*
> +        * If the MOV above was used directly as a ROP gadget we can
> +        * notice the lack of pinned bits in "val" and start the function
> +        * from the beginning to gain the cr4_pin bits for sure.
> +        */
> +       if (WARN_ONCE(cr4_pin && (val & cr4_pin) == 0,

Don't you mean `cr4_pin && (val & cr4_pin) != cr4_pin)`?

> +                     "cr4 pin bypass attempt?!\n"))
> +               goto again;
>  }

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] x86/asm: Pin sensitive CR4 bits
  2019-02-20  0:54 [PATCH] x86/asm: Pin sensitive CR4 bits Kees Cook
  2019-02-20  2:37 ` Jann Horn
@ 2019-02-20  8:14 ` Dominik Brodowski
  2019-02-20 17:01   ` Kees Cook
  1 sibling, 1 reply; 5+ messages in thread
From: Dominik Brodowski @ 2019-02-20  8:14 UTC (permalink / raw)
  To: Kees Cook; +Cc: Thomas Gleixner, linux-kernel, kernel-hardening, x86

On Tue, Feb 19, 2019 at 04:54:49PM -0800, Kees Cook wrote:
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index cb28e98a0659..7e0ea4470f8e 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -312,10 +312,16 @@ static __init int setup_disable_smep(char *arg)
>  }
>  __setup("nosmep", setup_disable_smep);
>  
> +volatile unsigned long cr4_pin __ro_after_init;
> +EXPORT_SYMBOL_GPL(cr4_pin);

Where is this export needed?

Thanks,
	Dominik

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] x86/asm: Pin sensitive CR4 bits
  2019-02-20  2:37 ` Jann Horn
@ 2019-02-20 17:00   ` Kees Cook
  0 siblings, 0 replies; 5+ messages in thread
From: Kees Cook @ 2019-02-20 17:00 UTC (permalink / raw)
  To: Jann Horn
  Cc: Thomas Gleixner, kernel list, Kernel Hardening, the arch/x86 maintainers

On Tue, Feb 19, 2019 at 6:37 PM Jann Horn <jannh@google.com> wrote:
>
> On Wed, Feb 20, 2019 at 1:55 AM Kees Cook <keescook@chromium.org> wrote:
> > +       if (WARN_ONCE(cr4_pin && (val & cr4_pin) == 0,
>
> Don't you mean `cr4_pin && (val & cr4_pin) != cr4_pin)`?

Whoops! Yes, thanks. :)

-- 
Kees Cook

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] x86/asm: Pin sensitive CR4 bits
  2019-02-20  8:14 ` Dominik Brodowski
@ 2019-02-20 17:01   ` Kees Cook
  0 siblings, 0 replies; 5+ messages in thread
From: Kees Cook @ 2019-02-20 17:01 UTC (permalink / raw)
  To: Dominik Brodowski; +Cc: Thomas Gleixner, LKML, Kernel Hardening, X86 ML

On Wed, Feb 20, 2019 at 12:15 AM Dominik Brodowski
<linux@dominikbrodowski.net> wrote:
>
> On Tue, Feb 19, 2019 at 04:54:49PM -0800, Kees Cook wrote:
> > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> > index cb28e98a0659..7e0ea4470f8e 100644
> > --- a/arch/x86/kernel/cpu/common.c
> > +++ b/arch/x86/kernel/cpu/common.c
> > @@ -312,10 +312,16 @@ static __init int setup_disable_smep(char *arg)
> >  }
> >  __setup("nosmep", setup_disable_smep);
> >
> > +volatile unsigned long cr4_pin __ro_after_init;
> > +EXPORT_SYMBOL_GPL(cr4_pin);
>
> Where is this export needed?

I use it in lkdtm (which I was going to land through the drivers tree,
but I haven't sent to Greg):

https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git/commit/?h=kspp/x86/cr4

-- 
Kees Cook

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2019-02-20 17:01 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2019-02-20  0:54 [PATCH] x86/asm: Pin sensitive CR4 bits Kees Cook
2019-02-20  2:37 ` Jann Horn
2019-02-20 17:00   ` Kees Cook
2019-02-20  8:14 ` Dominik Brodowski
2019-02-20 17:01   ` Kees Cook

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