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From: Greentime Hu <greentime.hu@sifive.com>
To: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector
Date: Mon, 4 Oct 2021 22:13:05 +0800	[thread overview]
Message-ID: <CAHCEeh+qLpGy9VRKgFw57zNs8J5BWYYArJpTobcz98+mKJW2yQ@mail.gmail.com> (raw)
In-Reply-To: <20210915222937.49066323@xhacker>

Jisheng Zhang <jszhang3@mail.ustc.edu.cn> 於 2021年9月15日 週三 下午10:36寫道:
>
> On Thu,  9 Sep 2021 01:45:32 +0800
> Greentime Hu <greentime.hu@sifive.com> wrote:
>
> > This patch replacees 2 instructions with 1 instruction to do the same thing
> > . rs1=x0 with rd != x0 is a special form of the instruction that sets vl to
> > MAXVL.
>
> Similarly, the vector.S is newly introduced in this patch set, so could
> this optimization be folded into the __vstate_save and __vstate_restore
> introduction patch? Or it's better to keep this optimizaion in commit log?
>
Yeah, I wanted to keep the optimization commit log before, but it's ok
if you think merge code is easier to read.
I'll merge this patch in the next version.

> >
> > Suggested-by: Andrew Waterman <andrew@sifive.com>
> > Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> > Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  arch/riscv/kernel/vector.S | 9 +++------
> >  1 file changed, 3 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
> > index 4f0c5a166e4e..f7223c81b11a 100644
> > --- a/arch/riscv/kernel/vector.S
> > +++ b/arch/riscv/kernel/vector.S
> > @@ -27,8 +27,7 @@
> >  #define x_vl     t2
> >  #define x_vcsr   t3
> >  #define incr     t4
> > -#define m_one    t5
> > -#define status   t6
> > +#define status   t5
> >
> >  ENTRY(__vstate_save)
> >       li      status, SR_VS
> > @@ -38,8 +37,7 @@ ENTRY(__vstate_save)
> >       csrr    x_vtype, CSR_VTYPE
> >       csrr    x_vl, CSR_VL
> >       csrr    x_vcsr, CSR_VCSR
> > -     li      m_one, -1
> > -     vsetvli incr, m_one, e8, m8
> > +     vsetvli incr, x0, e8, m8
> >       vse8.v   v0, (datap)
> >       add     datap, datap, incr
> >       vse8.v   v8, (datap)
> > @@ -61,8 +59,7 @@ ENTRY(__vstate_restore)
> >       li      status, SR_VS
> >       csrs    CSR_STATUS, status
> >
> > -     li      m_one, -1
> > -     vsetvli incr, m_one, e8, m8
> > +     vsetvli incr, x0, e8, m8
> >       vle8.v   v0, (datap)
> >       add     datap, datap, incr
> >       vle8.v   v8, (datap)
>
>

  reply	other threads:[~2021-10-04 14:13 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 17:45 [RFC PATCH v8 00/21] riscv: Add vector ISA support Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 05/21] riscv: Add vector feature to compile Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 07/21] riscv: Reset vector register Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 09/21] riscv: Add task switch support for vector Greentime Hu
2021-09-13 12:21   ` Darius Rad
2021-09-28 14:56     ` Greentime Hu
2021-09-29 13:28       ` Darius Rad
2021-10-01  2:46         ` Ley Foon Tan
2021-10-04 12:41           ` Greentime Hu
2021-10-05  2:12             ` Ley Foon Tan
2021-10-05 15:46               ` Greentime Hu
2021-10-07 10:10                 ` Ley Foon Tan
2021-10-04 12:36         ` Greentime Hu
2021-10-05 13:57           ` Darius Rad
2021-10-21  1:01             ` Paul Walmsley
2021-10-21 10:50               ` Darius Rad
2021-10-22  3:52                 ` Vincent Chen
2021-10-22 10:40                   ` Darius Rad
2021-10-25  4:47                     ` Greentime Hu
2021-10-25 16:22                       ` Darius Rad
2021-10-26  4:44                         ` Greentime Hu
2021-10-27 12:58                           ` Darius Rad
2021-11-09  9:49                             ` Greentime Hu
2021-11-09 19:21                               ` Darius Rad
2021-10-26 14:58                     ` Heiko Stübner
2021-09-08 17:45 ` [RFC PATCH v8 10/21] riscv: Add ptrace vector support Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-09-30  2:37   ` Ley Foon Tan
2021-09-08 17:45 ` [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 13/21] riscv: Add support for kernel mode vector Greentime Hu
2021-09-09  6:17   ` Christoph Hellwig
2021-09-08 17:45 ` [RFC PATCH v8 14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation Greentime Hu
2021-09-09  6:12   ` Christoph Hellwig
2021-09-28  7:00     ` Greentime Hu
2021-09-14  8:29   ` Ley Foon Tan
2021-09-28  7:01     ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 19/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector Greentime Hu
2021-09-15 14:29   ` Jisheng Zhang
2021-10-04 14:13     ` Greentime Hu [this message]
2021-09-08 17:45 ` [RFC PATCH v8 21/21] riscv: Turn has_vector into a static key if VECTOR=y Greentime Hu
2021-09-15 14:24   ` Jisheng Zhang
2021-10-04 15:04     ` Greentime Hu
2021-09-13  1:47 ` [RFC PATCH v8 00/21] riscv: Add vector ISA support Vincent Chen
2021-09-13 17:18 ` Vineet Gupta

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